IDT Switch Configuration and Status Registers
PES48T12G2 User Manual
16 - 12
April 5, 2013
S[13:12, 9:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control
General Purpose I/O Registers
GPIOFUNC0 - General Purpose I/O Function 0 (0x0A90)
Bit
Field
Field
Name
Type
Default
Value
Description
2:0
RXEQZ
RW
0x1
SWSticky
Receiver Equalization Zero.
Amplifies the high-frequency gain of
the equalizer. A value of 0x0 results in the smallest amount of high
frequency gain. A value of 0x7 results in the highest amount of
high frequency gain. Together with the other fields in this register,
the default value corresponds to a long, lossy channel.
Setting both RXEQZ and RXEQB to zero results in turning off
receiver equalization completely.
Refer to section Receiver Equalization Controls on page 7-15 for
further information of Receiver Equalization.
This field controls the receiver equalization for the lane(s) selected
by the Lane Select (LANESEL) field in the SerDes Control
(S[x]CTL) register. This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL register).
5:3
RXEQB
RW
0x7
SWSticky
Receive Equalization Boost.
Reduces the low-frequency gain of
the equalizer. A value of 0x0 results in the largest low frequency
gain and smallest amount of boost. A value of 0x7 results in the
smallest low frequency gain and largest amount of boost. Together
with the other fields in this register, the default value corresponds
to a long, lossy channel.
Setting both RXEQZ and RXEQB to zero results in turning off
receiver equalization completely.
Refer to section Receiver Equalization Controls on page 7-15 for
further information of Receiver Equalization.
This field controls the receiver equalization for the lane(s) selected
by the Lane Select (LANESEL) field in the SerDes Control
(S[x]CTL0) register. This value is SWSticky for all lanes (i.e., even
those not selected by the LANESEL field in the S[x]CTL0 register).
31:6
Reserved
RO
0x0
Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0
GPIOFUNC
RW
0x0
SWSticky
GPIO Function.
Each bit in this field controls the corresponding
GPIO pin. When set, the corresponding GPIO pin operates as the
selected alternate function. When a bit is cleared, the correspond-
ing GPIO pin operates as a general purpose I/O pin.
Bit x in this field corresponds to GPIO pin x.
Summary of Contents for 89HPES48T12G2
Page 14: ...IDT Table of Contents PES48T12G2 User Manual vi April 5 2013 Notes...
Page 22: ...IDT Register List PES48T12G2 User Manual xiv April 5 2013 Notes...
Page 38: ...IDT PES48T12G2 Device Overview PES48T12G2 User Manual 1 16 April 5 2013 Notes...
Page 64: ...IDT Reset and Initialization PES48T12G2 User Manual 5 8 April 5 2013 Notes...
Page 82: ...IDT Link Operation PES48T12G2 User Manual 6 18 April 5 2013 Notes...
Page 98: ...IDT SerDes PES48T12G2 User Manual 7 16 April 5 2013 Notes...
Page 118: ...IDT Theory of Operation PES48T12G2 User Manual 8 20 April 5 2013 Notes...
Page 152: ...IDT SMBus Interfaces PES48T12G2 User Manual 12 20 April 5 2013 Notes...
Page 158: ...IDT Multicast PES48T12G2 User Manual 13 6 April 5 2013 Notes...