IDT 89HPES48T12G2, User Manual

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IDT Clocking
PES48T12G2 User Manual 4 - 2 April 5, 2013
Notes The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot
configuration vector as shown in Table 4.1. This field determines the initial value of the Slot Clock Configu-
ration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls the
advertisement of whether or not the port uses the same reference clock source as the link partner. A one in
the SCLK field indicates that the port and its link partner use the same reference clock source. This is
defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field
indicates that the port and its link partner do not use the same reference clock source.
CLKMODE[1:0] Value in
Boot Configuration Vector
Port 0
SCLK
SCLK for Ports other
than Port 0
0 0 0
1 1 0
2 0 1
3 1 1
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State