9. Error Handling > PCI as Originating Interface
76
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
describes the PEB383 behavior on a PCI Delayed transaction that is forwarded by a bridge to
PCIe as a Memory Read request or an I/O Read/Write request, and the PCIe Interface returns a
completion with Unsupported Request or Completer Abort Completion status for the request.
9.3.1
Received PCI Errors
This section describes how the PEB383 handles PCI errors.
9.3.1.1
Uncorrectable Data Error on a Non-Posted Write Transaction PCI Mode
When the PEB383 receives non-posted write transaction that is addressed such that it crosses the
bridge, and the bridge detects an uncorrectable data error on its PCI Interface, it does the following:
1.
D_PE bit is set in
“PCI Secondary Status and I/O Limit and Base Register”
2.
“PCI Bridge Control and Interrupt Register”
, then the transaction is
discarded and is not forwarded to PCIe and the PERR# pin is asserted on the PCI bus
3.
“PCI Bridge Control and Interrupt Register”
, then the data is
forwarded to PCIe as a Poisoned TLP. M_DPE bit is set in
“PCI Control and Status Register”
if the
S_PERESP bit is set. The PERR# pin is not asserted on the PCI bus
4.
UDERR bit is set in
“PCIe Secondary Uncorrectable Error Status Register”
5.
Header is logged in the
“PCIe Secondary Header Log 1 Register”
and ERR_PTR is updated in the
“PCIe Secondary Error Capabilities and Control Register”
if UDERR Mask bit is clear in
Secondary Uncorrectable Error Mask Register”
and ERR_PTR is not valid
6.
Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of Uncorrectable
Data Error bit in
“PCIe Secondary Uncorrectable Error Severity Register”
, if UDERR Mask bit is
“PCIe Secondary Uncorrectable Error Mask Register”
and either SERR_EN bit is set in
“PCI Control and Status Register”
or FTL_ERR_EN/NFTL_ERR_EN bit is set in
7.
“PCI Control and Status Register”
if an error message (Fatal/Non-Fatal) is
generated and the SERR_EN bit is set
8.
FTL_ERR_DTD/NFTL_ERR_DTD bit is set in
“PCIe Device Control and Status Register”
Table 16: Error Forwarding Requirements for PCI Delayed Transaction
PCIe Completion Status
PCI Immediate Response
Master-Abort Mode = 1
PCI Immediate Response
Master-Abort Mode = 0
Unsupported Request (on Memory
or I/O Read)
Target Abort
Normal Completion, return
0xFFFF_FFFF
Unsupported Request (on I/O
Write)
Target Abort
Normal Completion
Completer Abort
Target Abort
Target Abort