1. Functional Overview > Device Architecture
9
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
PCI data that is destined for the PCIe fabric are subject to PCIe ordering rules. Data is pulled from the
appropriate queue:
•
Configuration register
•
Upstream posted write buffer
•
Upstream read request queue
•
Upstream read completion buffer
PCI transactions that are decoded for the PCIe address space are forwarded to the appropriate queue:
•
Upstream read request queue
•
Upstream posted write buffer
Transactions destined for downstream devices on the PCI bus, are subject to PCI ordering rules. Data is
pulled form the appropriate queue:
•
Downstream posted write buffer
•
Downstream read request queue
PCIe is a serialized protocol at the physical layer, and a packetized protocol at the data link layer. The
PCIe lane operates at 2.5 Gb symbol rate, or at 2.0 Gb data rate; the difference is a result of the 8/10b
coding process. The PEB383 uses the following processes to ensure the accurate and timely delivery of
data through the data link layer:
•
Credit-based flow control – Prevents data loss and congestion
•
ACK/noACK protocol and End-to-End CRC (ECRC) – Ensures reliable data delivery if bit errors
occur
•
Replay buffer – Replays packets that are not acknowledged by the receiver (NAK)
In contrast, PCI is a parallel data interface at the physical layer. PCI is a non-packetized protocol.
When a bus master starts a read or a write transaction, it indicates only the starting transaction address
to the target, and not the size of the read or write. In the case of a PCI write, which is initiated on the
PCI Interface and is destined for the root complex, the data is written into an upstream posted write
buffer in the PEB383. The end of the write transaction is signaled by the master on the PCI bus. Once
the write is completed the data can be forwarded to the PCIe Interface. If the posted write buffer is
about to overflow, the PEB383 indicates a retry/disconnect on the PCI bus. Once the posted write
buffer empties, the PEB383 can accept additional write transactions. The PEB383 will split write
transactions as required to meet PCIe constraints: to prevent a write crossing a 4-KB boundary; if byte
enables are used throughout the transaction; or if the quantity of data exceeds the maximum payload
size (see MAX_SIZE in
“PCIe Device Capabilities Register”
). The upstream posted write buffer is
managed as a simple FIFO.