14. Register Descriptions > Advanced Error Reporting Capability Registers
198
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
14.8.13
PCIe Secondary Uncorrectable Error Mask Register
Register name: PCIE_SEC_UERR_MASK
Reset value: 0x0000_17A8
Register offset: 0x130
Bits
7
6
5
4
3
2
1
0
31:24
Reserved
23:16
Reserved
15:08
Reserved
IB_ERR
SERR_AD
PERR_AD
DTDTE
UADD_
ERR
UATT_ERR
07:00
UDERR
USCM
USCE
Reserved
R_MA
R_TA
MA_SC
TA_SC
Bits
Name
Description
Type
Reset value
31:14
Reserved
Reserved
R
0x0000_0
13
IB_ERR
Internal Bridge Error Mask (No Header Log)
R/WS
0
12
SERR_AD
SERR# Assertion Detected Mask (No Header Log)
R/WS
1
11
PERR_AD
PERR# Assertion Detected Mask
R/WS
0
10
DTDTE
Delayed Transaction Discard Timer Expired Mask
(No Header Log)
R/WS
1
9
UADD_ERR
Uncorrectable Address Error Mask
R/WS
1
8
UATT_ERR
Uncorrectable Attribute Error Mask
R/WS
1
7
UDERR
Uncorrectable Data Error Mask
R/WS
1
6
USCM
Uncorrectable Split Completion Message Data Error Mask
a
a.
This bit has no effect on the PEB383 since it does not support PCI-X.
R/WS
0
5
USCE
Unexpected Split Completion Error Mask
R/WS
1
4
Reserved
Reserved
R
0
3
R_MA
Received Master-Abort Mask
R/WS
1
2
R_TA
Received Target-Abort Mask
R/WS
0
1
MA_SC
Master-Abort on Split Completion Mask
R/WS
0
0
TA_SC
Target-Abort on Split Completion Mask
R/WS
0