HP 1660CS, User Manual

Page: 303 / 347

Supplemental characteristics (logic analyzer)
Probes
Input resistance 100 k
Ω
,
±
2%
Input capacitance ~ 8 pF
Minimum voltage swing 500 mV, peak-to-peak
Threshold range
±
6.0 V, adjustable in 50-mV increments, CAT I
State analysis
State/Clock qualifiers 1660/61C - 6; 1662CS - 4; 1663CS - 2
Time tag resolution
*
8 ns or 0.1%, whichever is greater
Maximum time count
between states
34 seconds
Maximum state tag count
*
4.29 x 10
9
* Maximum state clock rate with time or state tags on is 100 MHz. When all pods are assigned to a state or
timing machine, time or state tags halve the memory depth.
Timing analysis
Sample period accuracy 0.01 % of sample period
Channel-to-channel skew 2 ns, typical
Time interval accuracy
±
[sample channel-to-channel skew
+(0.01%)(time reading)]
Triggering
Sequence speed 125 MHz, maximum
State sequence levels 12
Timing sequence levels 10
Maximum occurrence counter
value
1,048,575
Pattern recognizers 10
Maximum pattern width 136 channels in HP 1660CS, 102 channels in
HP 1661CS, 68 channels in HP 1662CS,
34 channels in HP 1663CS
Range recognizers 2
Specifications
Supplemental characteristics (logic analyzer)
11–6