HP 1660CS, User Manual

Page: 278 / 347

In addition to the storage qualification and counting functions, the acquisition
ASICs also perform master clocking functions. All six state acquisition clocks
are fed to each IC, and the ICs generate their own sample clocks. Every time
you select run, the ICs individually perform a clock optimization before data
is stored.
Clock optimization involves using programmable delays on board the IC to
position the master clock transition where valid data is captured. This
procedure greatly reduces the effects of channel-to-channel skew and other
propagation delays.
In the timing acquisition mode, an oscillator-driven clock circuit provides a
four-phase, 100-MHz clock signal to each of the acquisition ICs. For high
speed timing acquisition (100 MHz and faster), the sample period is
determined by the four-phase, 100-MHz clock signal.
For slower sample rates, one of the acquisition ICs divides the 100-MHz clock
signal to the appropriate sample rate. The sample clock is then fed to all
acquisition ICs.
Threshold
A precision octal DAC and precision op amp drivers make up the threshold
circuit. Each of the eight channels of the DAC is individually programmable
which allows you to set the thresholds of the individual pods. The 16 data
channels and the clock channel of each pod are all set to the same threshold
voltage.
Test and clock synchronization circuit
ECLinPS ICs are used in the test and clock synchronization circuit for
reliability and low channel-to-channel skew. Test patterns are generated and
sent to the comparators during software operation verification. The test
patterns are propagated across all data and clock channels and read by the
acquisition ASIC to ensure both the data and clock pipelines are operating
correctly.
The test and clock synchronization circuit also generates a four-phase,
100-MHz sample/synchronization signal for the acquisition ICs operating in
the timing acquisition mode. The synchronizing signal keeps the internal
clocking of the individual acquisition ASICs locked in step with the other
ASICs at fast sample rates. At slower sample rates, one of the acquisition ICs
divides the 100-MHz clock signal to the appropriate sample rate. The slow
speed sample clock is then used by all acquisition ICs.
The Analyzer Hardware
Logic acquisition board theory
9-27