Timing analyzer
When you configure a timing analyzer, the trigger sequence follows the
general outlines given previously. The trigger sequence of the timing analyzer
differs from the state analyzer in the following ways:
•
There are 10 levels available to build a trigger with.
•
The trigger term is always the last step.
•
The timing analyzer has two additional resources, Edge1 and Edge2.
•
Edge1 and Edge2 recognize occurrences of a glitch, rising edge, falling
edge, either edge, or no edge on a bit or ORed set of bits.
State analyzer
When you configure a state analyzer, the trigger sequence follows the general
outlines given previously. The trigger sequence of the state analyzer differs
from the timing analyzer in the following ways:
•
There are 12 levels available to build a trigger with.
•
The trigger term is never the last step.
•
The state analyzer cannot use Edge1 and Edge2.
The Trigger Sequence
Timing analyzer
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Summary of Contents for 1660CS
Page 5: ...Introduction iv ...
Page 16: ...1 Logic Analyzer Overview ...
Page 24: ...2 Connecting Peripherals ...
Page 33: ...2 10 ...
Page 34: ...3 Using the Logic Analyzer ...
Page 55: ...3 22 ...
Page 56: ...4 Using the Trigger Menu ...
Page 75: ...4 20 ...
Page 76: ...5 Triggering Examples ...
Page 109: ...5 34 ...
Page 110: ...6 File Management ...
Page 119: ...6 10 ...
Page 120: ...7 Reference ...
Page 221: ...7 102 ...
Page 222: ...8 System Performance Analysis SPA Software ...
Page 241: ...SPA Time Interval System Performance Analysis SPA Software SPA measurement processes 8 20 ...
Page 252: ...9 Concepts ...
Page 284: ...10 Troubleshooting ...
Page 298: ...11 Specifications ...
Page 311: ...11 14 ...
Page 312: ...12 Operator s Service ...
Page 324: ...Troubleshooting Flowchart 2 Troubleshooting To use the flowcharts 12 13 ...
Page 337: ...Glossary 4 ...