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Holtek HT32F50231 User Manual Download Page 452

Rev. 1.00 

452 of 486

July 31, 2018

32-Bit Arm

®

 Cortex

®

-M0+ MCU

HT32F50231/HT32F50241

21  Universal Synchronous 

Asynchronous Receiver T

ransmitter (USART)

21  Universal Synchronous 

Asynchronous Receiver T

ransmitter (USART)

USART Control Register – USRCR

The register specifies the serial parameters such as data length, parity and stop bit for the USART. It also 
contains the USART enable control bits together with the USART mode and data transfer mode selections.
Offset:

0x004

Reset value: 0x0000_0000

31

30

29

28

27

26

25

24

Reserved

Type/Reset

23

22

21

20

19

18

17

16

Reserved

Type/Reset

15

14

13

12

11

10

9

8

RTS

BCB

SPE

EPE

PBE

NSB

WLS

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7

6

5

4

3

2

1

0

Reserved URRXEN

URTXEN

HFCEN

TRSM

MODE

Type/Reset

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

Field

Descriptions

[15]

RTS

Request-To-Send Signal

0: Drive USART RTS pin to logic 1

1: Drive USART RTS pin to logic 0

Note that the RTS bit is used to control the USART RTS pin status when the HFCEN 
bit is reset.
When the HFCEN bit is set, this RTS bit is read only, which indicates the pin status 

that is controlled by hardware flow control function.

[14]

BCB

Break Control Bit
When this bit is set 1, the serial data output on the USART TX pin will be forced to 
the Spacing State (logic 0). This bit acts only on USART TX output pin and has no 
effect on the transmitter logic.

[13]

SPE

Stick Parity Enable

0: Disable stick parity 

1: Stick Parity bit is transmitted 

This bit is only available when the PBE bit is set to 1. If both the PBE and SPE bits 
are set to 1 and the EPE bit is cleared to 0, the transmitted parity bit will be stuck to 
1. However, when the PBE and SPE bits are set to 1 and also the EPE bit is set to 1, 
the transmitted parity bit will be stuck to 0.

[12]

EPE

Even Parity Enable

0: Odd number of logic 1’s are transmitted or checked in the data word and parity 

bits

1: Even number of logic 1’s are transmitted or checked in the data word and 

parity bits

This bit is only available when PBE is set to 1.

[11]

PBE

Parity Bit Enable

0: Parity bit is not generated (transmitted data) or checked (received data) during 

transfer

1: Parity bit is generated or checked during transfer

Note: When the WLS field is set to “10” to select the 9-bit data format, writing to the 

PBE bit has no effect.

Summary of Contents for HT32F50231

Page 1: ...Holtek 32 Bit Microcontroller with Arm Cortex M0 HT32F50231 HT32F50241 User Manual Revision V1 00 Date July 31 2018 ...

Page 2: ...ctional Descriptions 35 Flash Memory Map 35 Flash Memory Architecture 36 Booting Configuration 37 Page Erase 38 Mass Erase 39 Word Programming 40 Option Byte Description 41 Page Erase Program Protection 42 Security Protection 43 Register Map 44 Register Descriptions 45 Flash Target Address Register TADR 45 Flash Write Data Register WRDR 46 Flash Operation Command Register OCMR 47 Flash Operation C...

Page 3: ...rol Unit CKCU 70 Introduction 70 Features 72 Function Descriptions 72 High Speed External Crystal Oscillator HSE 72 High Speed Internal RC Oscillator HSI 73 Auto Trimming of High Speed Internal RC Oscillator HSI 73 Low Speed External Crystal Oscillator LSE 75 Low Speed Internal RC Oscillator LSI 75 Clock Ready Flag 75 System Clock CK_SYS Selection 75 HSE Clock Monitor 76 Clock Output Capability 76...

Page 4: ...ral Purpose I O GPIO 105 Introduction 105 Features 106 Functional Descriptions 106 Default GPIO Pin Configuration 106 General Purpose I O GPIO 106 GPIO Locking Mechanism 108 Register Map 108 Register Descriptions 109 Port A Data Direction Control Register PADIRCR 109 Port A Input Function Enable Control Register PAINER 110 Port A Pull Up Selection Register PAPUR 111 Port A Pull Down Selection Regi...

Page 5: ...Selection Register PCODR 133 Port C Output Current Drive Selection Register PCDRVR 134 Port C Lock Register PCLOCKR 135 Port C Data Input Register PCDINR 136 Port C Output Data Register PCDOUTR 136 Port C Output Set Reset Control Register PCSRR 137 Port C Output Reset Register PCRR 138 Port C Sink Current Enhanced Selection Register PCSCER 138 9 Alternate Function Input Output Control Unit AFIO 13...

Page 6: ...keup Polarity Register EXTIWAKUPPOLR 159 EXTI Interrupt Wakeup Flag Register EXTIWAKUPFLG 160 12 Analog to Digital Converter ADC 161 Introduction 161 Features 162 Function Descriptions 163 ADC Clock Setup 163 Channel Selection 163 Conversion Mode 163 Start Conversion on External Event 166 Sampling Time Setting 167 Data Format 167 Analog Watchdog 167 Interrupts 168 Register Map 169 Register Descrip...

Page 7: ...guration Register MDCFR 214 Timer Trigger Configuration Register TRCFR 217 Timer Counter Register CTR 218 Channel 0 Input Configuration Register CH0ICFR 219 Channel 1 Input Configuration Register CH1ICFR 220 Channel 2 Input Configuration Register CH2ICFR 222 Channel 3 Input Configuration Register CH3ICFR 223 Channel 0 Output Configuration Register CH0OCFR 224 Channel 1 Output Configuration Registe...

Page 8: ...ic PWM Mode 263 Timer Interconnection 263 Trigger Peripherals Start 265 Register Map 266 Register Descriptions 267 Timer Counter Configuration Register CNTCFR 267 Timer Mode Configuration Register MDCFR 268 Timer Trigger Configuration Register TRCFR 271 Timer Counter Register CTR 272 Channel 0 Output Configuration Register CH0OCFR 273 Channel 1 Output Configuration Register CH1OCFR 275 Channel 2 O...

Page 9: ...TMCR 295 BFTM Status Register BFTMSR 296 BFTM Counter Value Register BFTMCNTR 297 BFTM Compare Value Register BFTMCMPR 297 16 Motor Control Timer MCTM 298 Introduction 298 Features 299 Functional Descriptions 299 Counter Mode 299 Clock Controller 303 Trigger Controller 304 Slave Controller 305 Master Controller 307 Channel Controller 308 Input Stage 309 Output Stage 311 Update Management 322 Singl...

Page 10: ...ter Register CNTR 364 Timer Prescaler Register PSCR 365 Timer Counter Reload Register CRR 366 Timer Repetition Register REPR 366 Channel 0 Capture Compare Register CH0CCR 367 Channel 1 Capture Compare Register CH1CCR 368 Channel 2 Capture Compare Register CH2CCR 369 Channel 3 Capture Compare Register CH3CCR 370 Channel 0 Asymmetric Compare Register CH0ACR 371 Channel 1 Asymmetric Compare Register ...

Page 11: ...erial Interface 392 START and STOP Conditions 392 Data Validity 393 Addressing Format 394 Data Transfer and Acknowledge 396 Clock Synchronization 397 Arbitration 397 General Call Addressing 398 Bus Error 398 Address Mask Enable 398 Address Snoop 398 Operation Mode 398 Conditions of Holding SCL Line 404 I2 C Timeout Function 405 Register Map 405 Register Descriptions 406 I2 C Control Register I2CCR...

Page 12: ...IFO Time Out Counter Register SPIFTOCR 439 21 Universal Synchronous Asynchronous Receiver Transmitter USART 440 Introduction 440 Features 441 Functional Descriptions 441 Serial Data Format 441 Baud Rate Generation 442 Hardware Flow Control 443 IrDA 444 RS485 Mode 446 Synchronous Master Mode 448 Interrupts and Status 450 Register Map 450 Register Descriptions 451 USART Data Register USRDR 451 USART...

Page 13: ... 472 UART Divider Latch Register URDLR 474 UART Test Register URTSTR 475 23 Divider DIV 476 Introduction 476 Features 476 Functional Descriptions 476 Register Map 477 Register Descriptions 477 Divider Control Register CR 477 Dividend Data Register DDR 478 Divisor Data Register DSR 478 Quotient Data Register QTR 479 Remainder Data Register RMR 479 24 Cyclic Redundancy Check CRC 480 Introduction 480...

Page 14: ...d Control Signal True Table 107 Table 18 GPIO Register Map 108 Table 19 AFIO Selection for Peripheral Map Example 141 Table 20 AFIO Register Map 141 Table 21 Exception Types 146 Table 22 NVIC Register Map 148 Table 23 EXTI Register Map 152 Table 24 Data Format in ADCDR 15 0 167 Table 25 A D Converter Register Map 169 Table 26 Counting Direction and Encoding Signals 200 Table 27 Compare Match Outpu...

Page 15: ... 46 SPI Interface Format Setup 422 Table 47 SPI Mode Fault Trigger Conditions 427 Table 48 SPI Master Mode SEL Pin Status 427 Table 49 SPI Register Map 428 Table 50 Baud Rate Deviation Error Calculation CK_USART 20 MHz 443 Table 51 Baud Rate Deviation Error Calculation CK_USART 10 MHz 443 Table 52 USART Register Map 450 Table 53 Baud Rate Deviation Error Calculation CK_UART 20 MHz 467 Table 54 Bau...

Page 16: ...l Crystal Ceramic and Resonators for LSE 75 Figure 17 RSTCU Block Diagram 98 Figure 18 Power On Reset Sequence 99 Figure 19 GPIO Block Diagram 105 Figure 20 AFIO GPIO Control Signal 107 Figure 21 AFIO Block Diagram 139 Figure 22 EXTI Channel Input Selection 140 Figure 23 EXTI Block Diagram 149 Figure 24 EXTI Wakeup Event Management 150 Figure 25 EXTI Interrupt Debounce Function 151 Figure 26 ADC B...

Page 17: ...gned Mode 204 Figure 56 Update Event Setting Diagram 205 Figure 57 Single Pulse Mode 206 Figure 58 Immediate Active Mode Minimum Delay 207 Figure 59 Asymmetric PWM Mode versus Center aligned Counting Mode 208 Figure 60 Pausing MCTM using the GPTM CH0OREF Signal 209 Figure 61 Triggering MCTM with GPTM Update Event 210 Figure 62 Trigger GPTM and MCTM with the GPTM CH0 Input 211 Figure 63 PWM Block D...

Page 18: ...99 Trigger Controller Block 304 Figure 100 Slave Controller Diagram 305 Figure 101 MCTM in Restart Mode 305 Figure 102 MCTM in Pause Mode 306 Figure 103 MCTM in Trigger Mode 306 Figure 104 Master MCTMn and Slave GPTM Connection 307 Figure 105 MTO Selection 307 Figure 106 Capture Compare Block Diagram 308 Figure 107 Input Capture Mode 308 Figure 108 PWM Pulse Width Measurement Example 309 Figure 10...

Page 19: ...384 Figure 138 I2 C Module Block Diagram 391 Figure 139 START and STOP Condition 393 Figure 140 Data Validity 393 Figure 141 7 bit Addressing Mode 394 Figure 142 10 bit Addressing Write Transmit Mode 395 Figure 143 10 bits Addressing Read Receive Mode 395 Figure 144 I2 C Bus Acknowledge 396 Figure 145 Clock Synchronization during Arbitration 397 Figure 146 Two Master Arbitration Procedure 397 Figu...

Page 20: ... CTS Flow Control 444 Figure 168 IrDA Modulation and Demodulation 445 Figure 169 USART I O and IrDA Block Diagram 446 Figure 170 RS485 Interface and Waveform 447 Figure 171 USART Synchronous Transmission Example 448 Figure 172 Figure 11 8 bit Format USART Synchronous Waveform 449 Figure 173 UART Block Diagram 465 Figure 174 UART Serial Data Format 466 Figure 175 UART Clock CK_UART and Data Frame T...

Page 21: ...Tick timer and advanced debug support The devices operate at a frequency of up to 20 MHz for HT32F50231 50241 to obtain maximum efficiency It provides up to 64 KB of embedded Flash memory for code data storage and 8 KB of embedded SRAM memory for system operation and application program usage A variety of peripherals such as Hardware Divider DIV ADC I2 C USART UART SPI BFTM MCTM GPTM PWM CRC 16 32...

Page 22: ...l 20 MHz RC oscillator trimmed to 2 accuracy at 25 C operating temperature Internal 32 kHz RC oscillator Independent clock divider and gating bits for peripheral clock sources Power Management PWRCU Flexible power supply VDD power supply 2 5 V to 5 5 V VDDIO power supply for I O pins 1 8 V to 5 5 V Integrated 1 5 V LDO regulator for CPU core peripherals and memories power supply Three power domain...

Page 23: ...ncy division by any factor between 1 and 65536 Input Capture function Compare Match Output PWM waveform generation with Edge aligned and Center aligned Counting Modes Single Pulse Mode Output Encoder interface controller with two inputs using quadrature decoder Pulse Width Modulation PWM One 16 bit up down up down auto reload counter Up to 4 independent channels for each timer 16 bit programmable ...

Page 24: ...o hardware flow control mode RTS CTS IrDA SIR encoder and decoder RS485 mode with output enable control FIFO Depth 8 9 bits for both receiver and transmitter Universal Asynchronous Receiver Transmitter UART Asynchronous serial communication operating baud rate clock frequency of up to fPCLK 16 MHz Capability of full duplex communication Fully programmable characteristics of serial communication in...

Page 25: ...le 1 Features and Peripheral List Peripherals HT32F50231 HT32F50241 Main Flash KB 32 63 Option Bytes Flash KB 1 1 SRAM KB 4 8 Timers MCTM 1 GPTM 1 PWM 2 BFTM 2 WDT 1 RTC 1 Communication SPI 2 USART 1 UART 2 I2 C 2 Hardware Divider 1 CRC 16 32 1 EXTI 16 12 bit ADC Number of Channels 1 12 Channels GPIO Up to 40 CPU Frequency Up to 20 MHz Operating Voltage 2 5 V 5 5 V Operating Temperature 40 C 85 C ...

Page 26: ...y VDD15 MOSI MISO SCK SEL AF Flash Memory Interface LSI 32 kHz VDD VSS PWRCU nRST WAKEUP0 1 AF Powered by VDDA VDDA VSSA ADC_IN0 ADC_IN11 AF I2 C0 1 ADC 12 bit SAR ADC BFTM0 1 AHB to APB Bridge WDT GPIO PA PB 15 0 PC 7 0 AF TX RX I O Port Powered by VDD VSS VDD POR PDR BOD LVD XTALIN XTALOUT HSI 20 MHz HSE 4 20 MHz AF LDO 1 5 V GPTM CLDO CAP Powered by VDD SRAM X32KIN X32KOUT AF LSE 32 768 Hz RTCO...

Page 27: ...any value is allowed RW 19 18 SERDYIE PLLRDYIE RW 0 RW 0 Software can read and write to this bit RO 3 2 HSIRDY HSERDY RO 1 RO 0 Software can only read this bit A write operation will have no effect RC 1 0 PDF BAK_PORF RC 0 RC 1 Software can only read this bit Read operation will clear it to 0 automatically WC 3 2 SERDYF PLLRDYF WC 0 WC 0 Software can read this bit or clear it by writing 1 Writing ...

Page 28: ...emory map and up to 4 GB of memory space making the system flexible and extendable Arm Cortex M0 Processor The Cortex M0 processor is a very low gate count highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized low power processor The processor is based on the ARMv6 M architecture and supports Thumb instruction sets si...

Page 29: ...rocessor Debug Figure 2 Cortex M0 Block Diagram Bus Architecture The HT32F50231 50241 series devices consist of one master and four slaves in the bus architecture The Cortex M0 AHB Lite bus is the master while the internal SRAM access bus the internal Flash memory access bus the AHB peripherals access bus and the AHB to APB bridges are the slaves The single 32 bit AHB Lite system interface provide...

Page 30: ...e external interface to external AHB peripheral The processor accesses take priority over debug accesses The maximum address range of the Cortex M0 is 4 GB since it has 32 bit bus address width Additionally a pre defined memory map is provided by the Cortex M0 processor to reduce the software complexity of repeated implementation of different device vendors However some regions are used by the Arm...

Page 31: ..._0000 Reserved 0x2000_2000 8 KB APB peripherals 0x4000_0000 AHB peripherals 0x4008_0000 0x4010_0000 Private peripheral bus 0xE000_0000 Reserved 0xE010_0000 0xFFFF_FFFF 512 KB 512 KB USART 0x4000_0000 UART0 0x4000_1000 SPI0 0x4000_4000 0x4000_5000 I2 C0 ADC Reserved 0x4001_0000 EXTI 0x4002_3000 AFIO 0x4002_4000 WDT 0x4004_5000 0x4004_8000 0x4006_9000 0x4006_B000 0x4006_A000 0x4004_9000 0x4006_E000 ...

Page 32: ...2000 0x4004_3FFF Reserved 0x4004_4000 0x4004_4FFF SPI1 0x4004_5000 0x4004_7FFF Reserved 0x4004_8000 0x4004_8FFF I2 C0 0x4004_9000 0x4004_9FFF I2 C1 0x4004_A000 0x4006_7FFF Reserved 0x4006_8000 0x4006_8FFF WDT 0x4006_9000 0x4006_9FFF Reserved 0x4006_A000 0x4006_AFFF RTC PWRCU 0x4006_B000 0x4006_DFFF Reserved 0x4006_E000 0x4006_EFFF GPTM 0x4006_F000 0x4007_0FFF Reserved 0x4007_1000 0x4007_1FFF PWM1 ...

Page 33: ...nd word access operations AHB Peripherals The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF Some peripherals such as Clock Control Unit Reset Control Unit and Flash Memory Controller are connected to the AHB bus directly The AHB peripherals clocks are always enabled after a system reset Access to registers for these peripherals can be achieved directly via the AHB bus Note ...

Page 34: ...programming page erase are also provided for instruction data storage of Flash memory Flash Memory Controller Main Flash Memory Information Block Wait State Control Addressing Data Programming Control Control Register Pre fetch Buffer System Bus AHB Peripheral Bus Flash Figure 5 Flash Memory Controller Block Diagram Features Up to 64 KB of on chip Flash memory for storing instruction data and opti...

Page 35: ...ress from 0x1F00_0000 to 0x1F00_07FF is mapped to Boot Loader Block 2 KB Besides address 0x1FF0_0000 to 0x1FF0_03FF is the alias of Option Byte block 1 KB which locates at the last page of main Flash physically The memory mapping on system view is shown as below Main Flash Block User Application Reserved 0x0000_0000 Boot Loader Block Reserved Option Byte Reserved 0x1F00_0000 0x1FF0_0000 0x1FFF_FFF...

Page 36: ...k Name Address Page Protection Bit Size Main Flash Block Page 0 0x0000_0000 0x0000_03FF OB_PP 0 1 KB Page 1 0x0000_0400 0x0000_07FF OB_PP 1 1 KB Page 2 0x0000_0800 0x0000_0BFF OB_PP 2 1 KB Page 3 0x0000_0C00 0x0000_0FFF OB_PP 3 1 KB Page 60 0x0000_F000 0x0000_F3FF OB_PP 60 1 KB Page 61 0x0000_F400 0x0000_F7FF OB_PP 61 1 KB Page 62 0x0000_F800 0x0000_FBFF OB_PP 62 1 KB Page 63 Option Byte Physical ...

Page 37: ...e is shown in the following table Table 5 Booting Modes Booting Mode Selection Pin Mode Descriptions BOOT 0 Boot Loader The source of Vector is Boot Loader 1 Main Flash The source of Vector is main Flash The Flash Vector Mapping Control Register VMCR is provided to change the setting of the vector remapping temporarily after the chip reset The reset value of VMCR is determined by the BOOT pin stat...

Page 38: ... the operations have been completed by checking the value of OPCR register OPM 3 0 equals to 0xE Read and verify the page if required Note that a correct target page address must be confirmed The software may run out of control if the target erase page is being used to fetch code or access data The FMC will not provide any notification when this happens Additionally the page erase operation will b...

Page 39: ...it mass erase command to FMC by setting OPCR register Set OPM 3 0 0xA Wait until all operations have been finished by checking the value of OPCR register OPM 3 0 equals to 0xE Read and verify the Flash memory if required Since all Flash data will be reset as 0xFFFF_FFFF the mass erase operation can be implemented by the program that runs in the SRAM or by the debugging tool that accesses FMC regis...

Page 40: ...rations have been finished by checking the value of OPCR register OPM 3 0 equals to 0xE Read and verify the Flash memory if required Note that the word programming operation can not be successively applied to the same address twice Successive word programming operation to the same address must be separated by a page erase operation Besides the word program will be ignored on protected pages When t...

Page 41: ...bled 1 Flash Page n Erase Program Protection is disabled OB_PP n n 63 127 Reserved 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF OB_CP 0x010 Flash Security Protection OB_CP 0 0 Flash Security protection is enabled 1 Flash Security protection is disabled Option Byte Protection OB_CP 1 0 Option Byte protection is enabled 1 Option Byte protection is disabled OB_CP 31 2 Reserved 0xFFFF_FFFF OB_CK 0x...

Page 42: ...cts the pages that enable protection function Other pages are not affected 2 Main Flash page protection is configured by OB_PP 127 0 Option Byte is physically located at the last page of main Flash Option Byte page protection is configured by the OB_CP 1 bit 3 The page erase on Option Byte area can disable the page protection of main Flash 4 The page protection of Option Byte can only be disabled ...

Page 43: ...n means the software that is executed or booted from main Flash memory with the JTAG SW debugger being disconnected However the Option Byte area and page 0 are still under protection where the Program Page Erase operations are not accepted 2 The Mass erase operation can erase the Option Byte area and disable the security protection The following steps show the register access sequence for Security...

Page 44: ...r 0x0001_0000 PPSR 0x020 0x024 0x028 0x02C Flash Page Erase Program Protection Status Register 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX CPSR 0x030 Flash Security Protection Status Register 0x0000_000X VMCR 0x100 Flash Vector Mapping Control Register 0x0000_000X MDID 0x180 Flash Manufacturer and Device ID Register 0x0376_XXXX PNSR 0x184 Flash Page Number Status Register 0x0000_00XX PSSR 0x18...

Page 45: ...s 31 0 TADB Flash Target Address Bits For programming operations the TADR register specifies the address where the data is written Since the programming length is 32 bits the TADR shall be set as word aligned 4 bytes The TADB 1 0 will be ignored during programming operations For page erase operations the TADR register contains the page address which is going to be erased Since the page size is 1 K...

Page 46: ...eset value 0x0000_0000 31 30 29 28 27 26 25 24 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 WRDB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 WRDB Flash Write Data Bits The data va...

Page 47: ...4 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CMD Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 3 0 CMD Flash Operation Command The following table shows definitions of CMD 3 0 bits which specify the Flash operation If an invalid command is set and the IOCMIEN bit is set to 1 an Invalid Operation Comman...

Page 48: ...ration modes of the FMC Users can commit command which is set by the OCMR register to the FMC according to the address alias setting in the TADR register The contents of TADR WRDR and OCMR registers shall be prepared before setting this register After all the operation has been finished the OPM field will be set as 0xE or 0xF by the FMC hardware The Idle mode can be set when all the operations hav...

Page 49: ... ORFIEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 4 OREIEN Operation Error Interrupt Enable 0 Operation error interrupt is disabled 1 Operation error interrupt is enabled 3 IOCMIEN Invalid Operation Command Interrupt Enable 0 Invalid Operation Command interrupt is disabled 1 Invalid Operation Command interrupt is enabled 2 OBEIEN Option Byte Check Sum Error Interrupt Enable 0 Opt...

Page 50: ...an invalid erase program operation being applied to a protected page This bit is reset by hardware once a new flash operation command is committed 16 RORFF Raw Operation Finished Flag 0 The last flash operation command is not finished 1 The last flash operation command is finished The RORFF bit is directly connected to the Flash memory for debugging purpose 4 OREF Operation Error Flag 0 No flash o...

Page 51: ...that the Option Byte check sum value has to be correctly modified or the corresponding interrupt control is disabled Otherwise the interrupt will be continually generated 1 ITADF Invalid Target Address Flag 0 The target address is valid 1 The target address is invalid The data in the TADR field must be in the range from 0x0000_0000 to 0x1FFF_ FFFF Otherwise this bit will be set high and an ITAD in...

Page 52: ...ts Field Descriptions 127 0 PPSBn Page Erase Program Protection Status Bits n 0 127 PPSB n OB_PP n 0 The corresponding page is protected 1 The corresponding page is not protected The content of this register is not dynamically updated and will only be reloaded from the Option Byte when any kind of reset occurs The erase or program function of specific pages is not allowed when the corresponding bi...

Page 53: ...0000_000X 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved OBPSB CPSB Type Reset RO X RO X Bits Field Descriptions 1 OBPSB Option Byte Page Erase Program Protection Status Bit 0 The Option Byte page is protected 1 The Option Byte page is not protected The reset value of OBPSB is determined by ...

Page 54: ...0 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved VMCB Reserved Type Reset RW X Bits Field Descriptions 1 VMCB Vector Mapping Control Bit The VMCB bits is used to control the mapping source of first 4 word vector address 0x0 0xC The following table shows the vector mapping setting BOOT VMCB Descriptions Low 0 Boot Loader mode The vector mapping source is the boot loader area High 1 Main Flash mod...

Page 55: ...180 Reset value 0x0376_XXXX 31 30 29 28 27 26 25 24 MFID Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 23 22 21 20 19 18 17 16 MFID Type Reset RO 0 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 0 15 14 13 12 11 10 9 8 ChipID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 7 6 5 4 3 2 1 0 ChipID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 31 16 MFID Manufacturer ID Read as...

Page 56: ... RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 PNSB Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 PNSB Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 31 0 PNSB Flash Page Number Status Bits 0x0000_0010 Totally 16 pages for the on chip Flash memory device 0x0000_0020 Totally 32 pages for the on chip Flash memory device 0x0000_0040 Totally 64 pa...

Page 57: ...RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 PSSB Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 PSSB Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 7 6 5 4 3 2 1 0 PSSB Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 31 0 PSSB Status Bits of Flash Page Size 0x200 That means the page size is 512 Byte per page 0x400 That means t...

Page 58: ...t identity Offset 0x18C Reset value 0x000X_XXXX 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved ChipID Type Reset RO X RO X RO X RO X 15 14 13 12 11 10 9 8 ChipID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 7 6 5 4 3 2 1 0 ChipID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 19 0 ChipID Chip ID Read the complete 5 digital codes of th...

Page 59: ...lash Manufacture Privilege Information Block 31 30 29 28 27 26 25 24 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 23 22 21 20 19 18 17 16 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 15 14 13 12 11 10 9 8 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X 7 6 5 4 3 2 1 0 CID Type Reset RO X RO X RO X RO X RO X RO X RO X RO X Bits Field Descriptions 31 0 CIDn Custom ID Read ...

Page 60: ...and allow the application to achieve the best trade off between the conflicting demands of CPU operating time speed and power consumption The dash line in the Figure 11 indicates the power supply source of two digital power domains LDO Controller LSE LDOOFF DMOSON SLEEPDEEP nRST VDD15 VDD VDD15 1 5 V Domain VDD Domain LVD Low Voltage Detector POR PDR Power On Reset Power Down Reset LDO Voltage Reg...

Page 61: ...nd WAKEUP pins Detect a falling edge on the external reset pin nRST The control bit BODEN 1 and the supply power VDD VBOD To enter the Deep Sleep1 mode the PWRCU will request the LDO to operate in a low current mode LCM To enter the Deep Sleep2 mode the PWRCU will turn off the LDO and turn on the DMOS to supply an alternative 1 5 V power Voltage Regulator The voltage regulator LDO Depletion MOS DM...

Page 62: ... situation and then immediately issue a system reset when the BODRIS bit is cleared to 0 or issue an interrupt to notify the CPU to execute a power down procedure when the BODRIS bit is set to 1 For more details concerning the Brown Out Detector voltage VBOD refer to the electrical characteristics of the corresponding datasheet High Speed External Oscillator The High Speed External Oscillator HSE ...

Page 63: ...setting the AHBPRE field in the CKCU AHBCFGR register and the second is to turn off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application requirement Reducing the system clock speed before entering the sleep mode will also help to minimize power consumption Additionally there a...

Page 64: ...t mode while Deep Sleep2 turns off the LDO and uses a DMOS to keep 1 5 V power Once the PWRCU receives a wakeup event or an interrupt as shown in the preceding Mode Exiting table the LDO will then operate in normal mode and the high speed oscillator will be enabled Finally the CPU will return to Run mode to handle the wakeup interrupt if required A Low Voltage Detection also can be regarded as a w...

Page 65: ...re should read this bit to clear it after a system wake up from the power saving mode 8 WUPF0 External WAKEUP0 Pin Flag 0 The WAKEUP0 pin is not asserted 1 The WAKEUP0 pin is asserted This bit is set by hardware when the WAKEUP0 pin asserts and is cleared by software read Software should read this bit to clear it after a system wake up from the power saving mode 4 PORF Power On Reset Flag 0 VDD15 ...

Page 66: ...WAKEUP1 Signal Trigger Type WUP1TYPE 1 0 WAKEUP Signal Trigger Type 0 0 Positive edge Triggered 0 1 Negative edge Triggered 1 0 High level Sensitive 1 1 Low level Sensitive 17 16 WUP0TYPE WAKEUP0 Signal Trigger Type WUP0TYPE 1 0 WAKEUP Signal Trigger Type 0 0 Positive edge Triggered 0 1 Negative edge Triggered 1 0 High level Sensitive 1 1 Low level Sensitive 15 DMOSSTS Depletion MOS Status This bi...

Page 67: ...ion 1 Enable WAKEUP0 pin function The Software can set the WUP0EN bit as 1 to enable the WAKEUP0 pin function before entering the power saving mode When WUP0EN 1 a change on the WAKEUP0 pin wakes up the system from the power saving mode If the WAKEUP0 pin is active high this bit will set an input pull down mode The corresponding register bits which should be properly setup are the PBPD 12 to 1 in ...

Page 68: ... specifies flags enable bits and option bits for low voltage detector Offset 0x110 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved LVDS 2 LVDEWEN LVDIWEN LVDF LVDS 1 0 LVDEN Type Reset RW 0 RW 0 RW 0 RO 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved BODF Reserved BODRIS BODEN Type Reset RO 0 RW 0 RW 0 Bits Fi...

Page 69: ...lection For more details concerning the LVD programmable threshold voltage refer to the electrical characteristics of the corresponding datasheet 16 LVDEN Low Voltage Detect Enable 0 Disable Low Voltage Detect 1 Enable Low Voltage Detect Setting this bit to 1 will generate an LVD event when the VDD power is equal to or lower than the voltage set by LVDS bits Therefore when the LVD function is enab...

Page 70: ...onitor clock prescaler clock multiplexer and clock gating The clock of AHB APB and CPU are derived from system clock CK_SYS which can come from HSI HSE LSI and LSE Watchdog Timer and Real Time Clock RTC use either LSI or LSE as their clock source A variety of internal clocks can also be wired out through CKOUT for debugging purpose The clock monitor can be used to get clock failure detection of HS...

Page 71: ...C WDT Clock Monitor ADCEN CK_LSI HCLKS to SRAM HCLKF to Flash CM0PEN FMCEN SRAMEN Notes 1 This control bit is located at RTC Control Register RTCCR 2 The CK_IN signal is sourced from the external pin CKIN CK_AHB 000 001 010 011 100 101 110 CK_SYS SW 2 0 8 HCLKC to Cortex M0 CM0PEN control by H W Prescaler 1 32 CK_REF Divider 2 CKREFPRE HCLKBM to Bus Matrix BMEN HCLKAPB to APB Bridge APBEN Peripher...

Page 72: ... related hardware configuration is shown in the following figure The crystal with specific frequency must be placed across the two HSE pins XTALIN XTALOUT and the external components such as resistors and capacitors are necessary to make it oscillate properly The following guidelines are provided to improve the stability of the crystal circuit PCB layout The crystal oscillator should be located as...

Page 73: ...ators Software could configure the PSRCEN bit Power Saving Wakeup RC Clock Enable to 1 to force HSI clock to be system clock when wake up from Deep Sleep1 2 mode Subsequently the system clock is back to the original clock source if the original clock source ready flag is asserted This function can reduce the wakeup time when using HSE as system clock Auto Trimming of High Speed Internal RC Oscilla...

Page 74: ...ne 7 0 Auto Trimming Controller Fine Trimming Write Register 1 kHz 1 024 kHz 32 LSE 32 768 kHz External pin CKIN AT Counter Register Fine Trimming Read Register TMSEL Coarse Trimming Read Register Factory Trimming Bits 0 1 TRIMEN REFCLKSEL 1x 0x 0 1 AHB Bus ATCEN Auto Trimming HSI Block Diagram Figure 15 HSI Auto Trimming Block Diagram ...

Page 75: ...cause no external component is needed to make it oscillates The accuracy of the frequency of the low speed internal RC oscillator LSI is shown as the corresponding data sheet The LSIRDY flag in the Global Clock Status Register GCSR will indicate if the LSI clock is stable Clock Ready Flag CKCU provides clock ready flags for HSI HSE LSI and LSE to confirm those clocks are stable before using them a...

Page 76: ...or start up delay and be disabled when the HSE oscillator is stopped Once the HSE oscillator failure is detected the HSE oscillator will automatically be disabled The HSE clock stuck flag CKSF in the Global Clock Interrupt Register GCIR will be set and an event of main oscillator failure will be generated if the clock fail interrupt enable bit CKSIE in the GCIR is set This failure interrupt is con...

Page 77: ...nfiguration Register 0x0000_0001 AHBCCR 0x024 AHB Clock Control Register 0x0000_0065 APBCFGR 0x028 APB Configuration Register 0x0001_0000 APBCCR0 0x02C APB Clock Control Register 0 0x0000_0000 APBCCR1 0x030 APB Clock Control Register 1 0x0000_0000 CKST 0x034 Clock Source Status Register 0x0100_0003 APBPCSR0 0x038 APB Peripheral Clock Selection Register 0 0x0000_0000 APBPCSR1 0x03C APB Peripheral C...

Page 78: ...eld Descriptions 31 29 LPMOD Lower Power Mode Status 000 When Chip is in running mode 001 When Chip wants to enter Sleep mode 010 When Chip wants to enter Deep Sleep1 mode 011 When Chip wants to enter Deep Sleep2 mode Others Reserved Set and reset by hardware 15 11 CKREFPRE CK_REF Clock Prescaler Selection CK_REF CK_SYS CKREFPRE 1 2 00000 CK_REF CK_SYS 2 00001 CK_REF CK_SYS 4 11111 CK_REF CK_SYS 6...

Page 79: ...uction can start execution since the HSI clock is provided to MCU After the original clock source which is selected as CK_SYS before entering Deep Sleep1 2 mode is ready hardware will switch back the clock source as originally 16 CKMEN HSE Clock Monitor Enable 0 Disable External crystal oscillator clock monitor 1 Enable External crystal oscillator clock monitor When hardware detects HSE clock stuc...

Page 80: ... system clock These bits are set and reset by software to select CK_SYS source If the HSE oscillator is used directly or indirectly as the system clock and the HSE clock monitor function is enabled once the HSE failure is detected these bits will be set by hardware to force HSI b011 as the system clock Note When switch the system clock using the SW bits the system clock is not immediately switched...

Page 81: ...llator clock is not ready 1 Internal 32 kHz RC oscillator clock is ready Set by hardware to indicate that the LSI is stable to be used 4 LSERDY External Low Speed Clock Ready Flag 0 External 32 768 kHz RC oscillator clock is not ready 1 External 32 768 kHz RC oscillator clock is ready Set by hardware to indicate that the LSE is stable to be used 3 HSIRDY Internal High Speed Clock Ready Flag 0 Inte...

Page 82: ... 18 17 16 Reserved CKSIE Type Reset RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CKSF Type Reset WC 0 Bits Field Descriptions 16 CKSIE Clock Stuck Interrupt Enable 0 Disable clock fail interrupt 1 Enable clock fail interrupt Set and reset by software to enable disable interrupt caused by clock monitor 0 CKSF Clock Stuck Interrupt Flag 0 Clock works normally 1 HSE clock i...

Page 83: ...4 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved AHBPRE Type Reset RW 0 RW 0 RW 1 Bits Field Descriptions 2 0 AHBPRE AHB Pre scaler 000 CK_AHB CK_SYS 001 CK_AHB CK_SYS 2 010 CK_AHB CK_SYS 4 011 CK_AHB CK_SYS 8 100 CK_AHB CK_SYS 16 101 CK_AHB CK_SYS 32 110 CK_AHB CK_SYS 32 111 CK_AHB CK_SYS 32 Set and reset by softw...

Page 84: ...eset by software 18 PCEN GPIO Port C Clock Enable 0 Port C clock is disabled 1 Port C clock is enabled Set and reset by software 17 PBEN GPIO Port B Clock Enable 0 Port B clock is disabled 1 Port B clock is enabled Set and reset by software 16 PAEN GPIO Port A Clock Enable 0 Port A clock is disabled 1 Port A clock is enabled Set and reset by software 13 CRCEN CRC Module Clock Enable 0 CRC clock is...

Page 85: ... Controller Clock Enable 0 FMC clock is automatically disabled by hardware during Sleep mode 1 FMC clock is always enabled during Sleep mode Set and reset by software Users can set FMCEN as 0 to reduce power consumption if the Flash Memory is unused during Sleep mode APB Configuration Register APBCFGR This register specifies the frequency of ADC conversion clock Offset 0x028 Reset value 0x0001_000...

Page 86: ...15 EXTIEN External Interrupt Clock Enable 0 EXTI clock is disabled 1 EXTI clock is enabled Set and reset by software 14 AFIOEN Alternate Function I O Clock Enable 0 AFIO clock is disabled 1 AFIO clock is enabled Set and reset by software 11 UR1EN UART1 Clock Enable 0 UART1 clock is disabled 1 UART1 clock is enabled Set and reset by software 10 UR0EN UART0 Clock Enable 0 UART0 clock is disabled 1 U...

Page 87: ...ype Reset RW 0 23 22 21 20 19 18 17 16 Reserved BFTM1EN BFTM0EN Type Reset RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved PWM1EN PWM0EN Reserved GPTMEN Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved VDDREN Reserved WDTREN Reserved MCTMEN Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 24 ADCCEN ADC Controller Clock Enable 0 ADC clock is disabled 1 ADC clock is enabled Set and reset by software 17 ...

Page 88: ...k is disabled 1 GPTM clock is enabled Set and reset by software 6 VDDREN VDD Domain Clock Enable for Registers Access 0 Register access clock is disabled 1 Register access clock is enabled Set and reset by software 4 WDTREN Watchdog Timer Clock Enable for Registers Access 0 Register access clock is disabled 1 Register access clock is enabled Set and reset by software 0 MCTMEN MCTM Clock Enable 0 M...

Page 89: ...6 5 4 3 2 1 0 Reserved CKSWST Type Reset RO 0 RO 1 RO 1 Bits Field Descriptions 26 24 HSIST Internal High Speed Clock Occupation Status CK_HSI xx1 HSI is used by System Clock CK_SYS SW 0x3 x1x Reserved 1xx HSI is used by Clock Monitor 17 16 HSEST External High Speed Clock Occupation Status CK_HSE x1 HSE is used by System Clock CK_SYS SW 0x2 1x Reserved 2 0 CKSWST Clock Switch Status 00x Reserved 0...

Page 90: ...RW 0 Bits Field Descriptions 31 30 UR1PCLK UART1 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 29 28 UR0PCLK UART0 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 25 24 USRPCLK USART Peripheral Clock Selection 00 P...

Page 91: ... CPU clock 7 6 SPI1PCLK SPI1 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 5 4 SPI0PCLK SPI0 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 3 2 I2C1PCLK I2 C1 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_A...

Page 92: ...ss Clock Selection 00 PCLK CK_AHB 4 01 PCLK CK_AHB 8 10 PCLK CK_AHB 16 11 PCLK CK_AHB 32 PCLK Peripheral Clock CK_AHB AHB and CPU clock 13 12 WDTRPCLK WDT Register Access Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 5 4 ADCCPCLK ADC Controller Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AH...

Page 93: ...ons in voltage and temperature that influence the frequency of the HSI It can be programmed by software or automatically adjusted by the Auto Trimming Controller ATC with an external reference clock 7 FLOCK Frequency Lock 0 HSI frequency is not trimmed into target range 1 HSI frequency is trimmed into target range 6 5 REFCLKSEL Reference Clock Selection 0x Select 32 768 kHz external low speed cloc...

Page 94: ...C hardware or user programming HSI Auto Trimming Counter Register HSIATCR This register contains the counter value of the HSI auto trimming controller Offset 0x044 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ATCNT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 ATCNT Type Reset RO 0 RO 0 RO ...

Page 95: ...23 22 21 20 19 18 17 16 Reserved PWM1PCLK PWM0PCLK Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved Type Reset Bits Field Descriptions 19 18 PWM1PCLK PWM1 Peripheral Clock Selection 00 PCLK CK_AHB 01 PCLK CK_AHB 2 10 PCLK CK_AHB 4 11 PCLK CK_AHB 8 PCLK Peripheral Clock CK_AHB AHB and CPU clock 17 16 PWM0PCLK PWM0 Peripheral Clock Selection 00 PCLK C...

Page 96: ...t and reset by software 30 DBPWM0 PWM0 Debug Mode Enable 0 PWM0 counter continues to count even if the core is halted 1 PWM0 counter is stopped when the core is halted Set and reset by software 19 DBUR1 UART1 Debug Mode Enable 0 Same behavior as in normal mode 1 UART1 timeout is frozen when the core is halted Set and reset by software 18 DBUR0 UART0 Debug Mode Enable 0 Same behavior as in normal m...

Page 97: ...e 0 Same behavior as in normal mode 1 USART timeout is frozen when the core is halted Set and reset by software 6 DBGPTM GPTM Debug Mode Enable 0 GPTM counter continues to count even if the core is halted 1 GPTM counter is stopped when the core is halted Set and reset by software 4 DBMCTM MCTM Debug Mode Enable 0 MCTM counter continues even if the core is halted 1 MCTM counter is stopped when the ...

Page 98: ...ebug port controller The resets can be triggered by an external signal internal events and the reset generators More information about these resets will be described in the following section 1 5 V Core Power RESET Filter Filter Delay PORRESETn WDT_RSTn SYSRESETREQ nRST VDD15 POR15 HRESETn Reset generator WDTRST Reset generator USRRST WDT reset USART reset VDD Domain POR Filter POR VDD PWCURST RTC ...

Page 99: ...on refer to the PWRCU chapter PORRESETn SYSRESETn VDD VDD15 t1 t2 t3 t1 25 μs Typical t2 100 μs t3 150 μs This timing is dependent on the internal LDO regulator output capacitor value Figure 18 Power On Reset Sequence System Reset A system reset is generated by a power on reset PORRESETn a Watchdog Timer reset WDT_RSTn nRST pin or a software reset SYSRESETREQ event For more information about SYSRE...

Page 100: ...28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved PORSTF WDTRSTF EXTRSTF NVICRSTF Type Reset WC 1 WC 0 WC 0 WC 0 Bits Field Descriptions 3 PORSTF Core 1 5 V Power On Reset Flag 0 No POR occurred 1 POR occurred This bit is set by hardware when a power on reset occurs and reset by writing 1 into it 2 WDTR...

Page 101: ...rved Type Reset 15 14 13 12 11 10 9 8 Reserved PCRST PBRST PARST Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CRCRST Reserved Type Reset RW 0 Bits Field Descriptions 24 DIVRST Divider Reset Control 0 No reset 1 Reset Divider This bit is set by software and cleared to 0 by hardware automatically 10 PCRST GPIO Port C Reset Control 0 No reset 1 Reset Port C This bit is set by software and cleared to 0 b...

Page 102: ...XTI This bit is set by software and cleared to 0 by hardware automatically 14 AFIORST Alternate Function I O Reset Control 0 No reset 1 Reset Alternate Function I O This bit is set by software and cleared to 0 by hardware automatically 11 UR1RST UART1 Reset Control 0 No reset 1 Reset UART1 This bit is set by software and cleared to 0 by hardware automatically 10 UR0RST UART0 Reset Control 0 No res...

Page 103: ...set RW 0 23 22 21 20 19 18 17 16 Reserved BFTM1RST BFTM0RST Type Reset RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved PWM1RST PWM0RST Reserved GPTMRST Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved WDTRST Reserved MCTMRST Type Reset RW 0 RW 0 Bits Field Descriptions 24 ADCRST A D Converter Reset Control 0 No reset 1 Reset A D Converter This bit is set by software and cleared to 0 by hardware automat...

Page 104: ...ed to 0 by hardware automatically 8 GPTMRST GPTM Reset Control 0 No reset 1 Reset GPTM This bit is set by software and cleared to 0 by hardware automatically 4 WDTRST Watchdog Timer Reset Control 0 No reset 1 Reset Watchdog Timer This bit is set by software and cleared to 0 by hardware automatically 0 MCTMRST MCTM Reset Control 0 No reset 1 Reset MCTM This bit is set by software and cleared to 0 b...

Page 105: ...ecification and package type Plase refer the device data sheet for detail information The GPIO ports are pin shared with other alternative functions AFs to obtain maximum flexibility on the package pins The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardless of the AF input or output pins The external interrupts on the GPIO pins of the device ...

Page 106: ...ins can be configured as inputs or outputs via the data direction control registers PxDIRCR where x A C When the GPIO pins are configured as input pins the data on the external pads can be read if the enable bits in the input enable function register PxINER are set The GPIO pull up pull down registers PxPUR PxPDR can be configured to fit specific applications When the pull up and pull down functio...

Page 107: ... Enable PxDVn x A C Output Drive PxODn x A C Open Drain PxPDn PxPUn x A C Pull Down Up PxCFGn x A C AFIO Configuration Table 17 AFIO GPIO and I O Pad Control Signal True Table Type AFIO GPIO PAD ADENAFIO OENAFIO IENAFIO PxDIRn PxINENn ADEN OEN IEN GPIO Input Note 1 1 1 0 1 1 1 0 GPIO Output Note 1 1 1 1 0 1 if need 1 0 1 0 AFIO Input 1 1 0 0 X 1 1 0 AFIO Output 1 0 1 X 0 1 if need 1 0 1 0 ADC Inpu...

Page 108: ...Data Input Register 0x0000_3200 PADOUTR 0x020 Port A Data Output Register 0x0000_0000 PASRR 0x024 Port A Output Set Reset Control Register 0x0000_0000 PARR 0x028 Port A Output Reset Control Register 0x0000_0000 PASCER 0x02C Port A Sink Current Enhanced Selection Register 0x0000_0000 GPIO B Base Address 0x400B_2000 PBDIRCR 0x000 Port B Data Direction Control Register 0x0000_0000 PBINER 0x004 Port B...

Page 109: ... 0x02C Port C Sink Current Enhanced Selection Register 0x0000_0000 Register Descriptions Port A Data Direction Control Register PADIRCR This register is used to control the direction of the GPIO Port A pin as input or output Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PADIR Type Reset RW 0 RW 0 R...

Page 110: ...e Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 0 7 6 5 4 3 2 1 0 PAINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAINENn GPIO Port A pin n Input Enable Control Bits n 0 15 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input function is disa...

Page 111: ...8 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAPU Type Reset RW 0 RW 0 RW 1 RW 1 RW 0 RW 0 RW 1 RW 0 7 6 5 4 3 2 1 0 PAPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAPUn GPIO Port A pin n Pull Up Selection Control Bits n 0 15 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled Note When the pull up and pull down functions are both ena...

Page 112: ... 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PAPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAPDn GPIO Port A pin n Pull Down Selection Control Bits n 0 15 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled Note When the pull up and pull down functions are bot...

Page 113: ...30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PAOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PAOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PAODn GPIO Port A pin n Open Drain Selection Control Bits n 0 15 0 Pin n Open Drain output is disabled The output type is CMOS output 1 ...

Page 114: ... 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 PADV11 PADV10 PADV9 PADV8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 PADV7 PADV6 PADV5 PADV4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PADV3 PADV2 PADV1 PADV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PADVn 1 0 GPIO Port A pin n Output Drive Current Selec...

Page 115: ... equal to 0x5FA0 any write operations on the PALOCKR register will be aborted The result of a read operation on the PALKEY field returns the GPIO Port A Lock Status which indicates whether the GPIO Port A is locked or not If the read value of the PALKEY field is 0 this indicates that the GPIO Port A Lock function is disabled Otherwise it indicates that the GPIO Port A Lock function is enabled as t...

Page 116: ...O 0 RO 0 Bits Field Descriptions 15 0 PADINn GPIO Port A pin n Data Input Bits n 0 15 0 The input data of pin n is 0 1 The input data of pin n is 1 Port A Output Data Register PADOUTR This register specifies the GPIO Port A output data Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PADOUT Type Reset...

Page 117: ...T Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 PASET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 31 16 PARSTn GPIO Port A pin n Output Reset Control Bits n 0 15 0 No effect on the PADOUTn bit 1 Reset the PADOUTn bit Note that when the PARSTn bit in this register or and the PARSTn bit in the PARR register is enabled the reset function on the PADO...

Page 118: ... n Output Reset Control Bits n 0 15 0 No effect on the PADOUTn bit 1 Reset the PADOUTn bit Port A Sink Current Enhanced Selection Register PASCER This register specifies the GPIO Port A enhanced sink driving current Offset 0x02C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PASCE15 PASCE14 PASCE13 PASCE12 PASCE...

Page 119: ...nput or output Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBDIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBDIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBDIRn GPIO Port B pin n Direction Control Bits n 0 15 0 Pin n is in input mode...

Page 120: ...e Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBINENn GPIO Port B pin n Input Enable Control Bits n 0 15 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input function is disa...

Page 121: ...8 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBPUn GPIO Port B pin n Pull Up Selection Control Bits n 0 15 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled Note When the pull up and pull down functions are both ena...

Page 122: ... 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBPDn GPIO Port B pin n Pull Down Selection Control Bits n 0 15 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled Note When the pull up and pull down functions are bot...

Page 123: ...30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PBODn GPIO Port B pin n Open Drain Selection Control Bits n 0 15 0 Pin n Open Drain output is disabled The output type is CMOS output 1 ...

Page 124: ... 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 PBDV11 PBDV10 PBDV9 PBDV8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 PBDV7 PBDV6 PBDV5 PBDV4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PBDV3 PBDV2 PBDV1 PBDV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PBDVn 1 0 GPIO Port B pin n Output Drive Current Selec...

Page 125: ...ot equal to 0x5FA0 any write operations on the PBLOCKR register will be aborted The result of a read operation on the PBLKEY field returns the GPIO Port B Lock Status which indicates whether the GPIO Port B is locked or not If the read value of the PBLKEY field is 0 this indicates that the GPIO Port B Lock function is disabled Otherwise it indicates that the GPIO Port B Lock function is enabled as...

Page 126: ...s Field Descriptions 15 0 PBDINn GPIO Port B pin n Data Input Bits n 0 15 0 The input data of corresponding pin is 0 1 The input data of corresponding pin is 1 Port B Output Data Register PBDOUTR This register specifies the GPIO Port B output data Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBDOU...

Page 127: ...T Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 PBSET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 31 16 PBRSTn GPIO Port B pin n Output Reset Control Bits n 0 15 0 No effect on the PBDOUTn bit 1 Reset the PBDOUTn bit Note that when the PBRSTn bit in this register or and the PBRSTn bit in the PBRR register is enabled the reset function on the PBDO...

Page 128: ... n Output Reset Control Bits n 0 15 0 No effect on the PBDOUTn bit 1 Reset the PBDOUTn bit Port B Sink Current Enhanced Selection Register PBSCER This register specifies the GPIO Port B enhanced sink driving current Offset 0x02C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PBSCE15 PBSCE14 PBSCE13 PBSCE12 PBSCE...

Page 129: ...PIO Port C pin as input or output Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 PCDIR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 PCDIRn GPIO Port C pin n Direction Control Bits n 0 7 0 Pin n is in input mode 1 Pin n is in outpu...

Page 130: ...6 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 PCINEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 PCINENn GPIO Port C pin n Input Enable Control Bits n 0 7 0 Pin n input function is disabled 1 Pin n input function is enabled When the pin n input function is disabled the input Schmi...

Page 131: ...et 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 PCPU Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 PCPUn GPIO Port C pin n Pull Up Selection Control Bits n 0 7 0 Pin n pull up function is disabled 1 Pin n pull up function is enabled Note When the pull up and pull down functions are both enabled the pull up fu...

Page 132: ...t 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 PCPD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 PCPDn GPIO Port C pin n Pull Down Selection Control Bits n 0 7 0 Pin n pull down function is disabled 1 Pin n pull down function is enabled Note When the pull up and pull down functions are both enabled the pull ...

Page 133: ...lue 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 PCOD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 PCODn GPIO Port C pin n Open Drain Selection Control Bits n 0 7 0 Pin n Open Drain output is disabled The output type is CMOS output 1 Pin n Open Drain ou...

Page 134: ... 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PCDV7 PCDV6 PCDV5 PCDV4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PCDV3 PCDV2 PCDV1 PCDV0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PCDVn 1 0 GPIO Port C pin n Output Drive Current Selection Control Bits n 0 7 00 4 mA source sink current 01 8 m...

Page 135: ...0 any write operations on the PCLOCKR register will be aborted The result of a read operation on the PCLKEY field returns the GPIO Port C Lock Status which indicates whether the GPIO Port C is locked or not If the read value of the PCLKEY field is 0 this indicates that the GPIO Port C Lock function is disabled Otherwise it indicates that the GPIO Port C Lock function is enabled as the read value i...

Page 136: ...Bits Field Descriptions 7 0 PCDINn GPIO Port C pin n Data Input Bits n 0 7 0 The input data of corresponding pin is 0 1 The input data of corresponding pin is 1 Port C Output Data Register PCDOUTR This register specifies the GPIO Port C output data Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Rese...

Page 137: ...served Type Reset 7 6 5 4 3 2 1 0 PCSET Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 23 16 PCRSTn GPIO Port C pin n Output Reset Control Bits n 0 7 0 No effect on the PCDOUTn bit 1 Reset the PCDOUTn bit Note that when the PCRSTn bit in this register or and the PCRSTn bit in the PCRR register is enabled the reset function on the PCDOUTn bit will take effect 7 0 PCSETn ...

Page 138: ...ns 7 0 PCRSTn GPIO Port C pin n Output Reset Control Bits n 0 7 0 No effect on the PCDOUTn bit 1 Reset the PCDOUTn bit Port C Sink Current Enhanced Selection Register PCSCER This register specifies the GPIO Port C enhanced sink driving current Offset 0x02C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ...

Page 139: ... locations can be selected by using the peripheral I O remapping mechanism Additionally various GPIO pins can be selected to be the EXTI interrupt line by setting the EXTInPIN 3 0 field in the ESSRn register to trigger an interrupt or event Please refer to the EXTI section for more details AFIO Configuration Registers PxLOCKR GPIO Module GPIOx APB Interface Peripheral IP I O AFIO Configuration Reg...

Page 140: ...nnected to the 16 EXTI lines as shown in the accompanying figure For example users can set the EXTI0PIN 3 0 field in the ESSR0 register to b0000 to select the GPIO PA0 pin as EXTI line 0 input Since not all the pins of the Port A C are available in all package types please refer to the pin assignment section for detailed pin information The setting of the EXTInPIN 3 0 field is invalid when the cor...

Page 141: ...ernate Function 2 AF2 PxCFGn 3 0 1110 Alternate Function 14 AF14 PxCFGn 3 0 1111 Alternate Function 15 AF15 Table 19 AFIO Selection for Peripheral Map Example AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 System Default GPIO ADC N A GPTM MCTM SPI USART UART I2 C N A N A N A N A N A PWM N A System Other Lock Mechanism The device also offers a lock function to lock the AFIO c...

Page 142: ...RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 EXTI3PIN EXTI2PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI1PIN EXTI0PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 EXTInPIN 3 0 EXTIn Pin Selection n 0 7 0000 PA Bit n is selected as EXTIn source signal 0001 PB Bit n is selected as EXTIn source signal 0010 PC Bit n is selected as EXTIn sou...

Page 143: ...RW 0 RW 0 15 14 13 12 11 10 9 8 EXTI11PIN EXTI10PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI9PIN EXTI8PIN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 EXTInPIN 3 0 EXTIn Pin Selection n 8 15 0000 PA Bit n is selected as EXTIn source signal 0001 PB Bit n is selected as EXTIn source signal 0010 PC Bit n is selected as EXTIn source sig...

Page 144: ...FG3 PxCFG2 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PxCFG1 PxCFG0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PxCFGn 3 0 Alternate function selection for port x pin n n 0 7 0000 Port x pin n is selected as AF0 0001 Port x pin n is selected as AF1 1110 Port x pin n is selected as AF14 1111 Port x pin n is selected as AF15 If the pin is s...

Page 145: ...xCFG11 PxCFG10 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PxCFG9 PxCFG8 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 PxCFGn 3 0 Alternate function selection for port x pin n n 8 15 0000 Port x pin n is selected as AF0 0001 Port x pin n is selected as AF1 1110 Port x pin n is selected as AF14 1111 Port x pin n is selected as AF15 If the pin...

Page 146: ...ble 21 Exception Types Interrupt Number Exception Number Exception Type Priority Vector Address Description 0 0x000 Initial Stack Point value 1 Reset 3 Highest 0x004 Reset 14 2 NMI 2 0x008 Non Maskable Interrupt The clock stuck interrupt signal clock monitor function provided by Clock Control Unit is connected to the NMI input 13 3 Hard Fault 1 0x00C All fault classes 4 10 Reserved 5 11 SVCall Con...

Page 147: ...obal interrupt 26 42 UART1 Configurable 2 0x0A8 UART1 global interrupt 27 43 Reserved 0x0AC 28 44 Reserved 0x0B0 29 45 Reserved 0x0B4 30 46 Reserved 0x0B8 31 47 Reserved 0x0BC Notes 1 The exception priority can be changed using the NVIC System Handler Priority Registers For more information refer to the Arm Cortex M0 Devices Generic User Guide document 2 The interrupt priority can be changed using...

Page 148: ...CER 0x180 Interrupt Clear Enable Register 0x0000_0000 NVIC_ISPR 0x200 Interrupt Set Pending Register 0x0000_0000 NVIC_ICPR 0x280 Interrupt Clear Pending Register 0x0000_0000 NVIC_IPR0 0x400 Interrupt 0 3 Priority Register 0x0000_0000 NVIC_IPR1 0x404 Interrupt 4 7 Priority Register 0x0000_0000 NVIC_IPR2 0x408 Interrupt 8 11 Priority Register 0x0000_0000 NVIC_IPR3 0x40C Interrupt 12 15 Priority Regi...

Page 149: ...and the corresponding EXTI wakeup enable bit is set Each EXTI line can also be masked independently Debounce Deglitch Edge Level Detection Polarity Detection Polarity Control EXTInWPOL Edge Level Control SRCnTYPE 2 0 EXTI Interrupt Control Status EXTI Event Control Status Software Activate EXTInSC EXTI 0 EXTI 15 DBnCNT 15 0 16 16 16 16 16 16 16 16 16 16 High or Low level High or Low level Rising o...

Page 150: ...ble bit in the corresponding peripheral the wakeup signal will be sent to the CPU and the CKCU via the EXTI controller when the corresponding wakeup event occurs Additionally the software can enable the event wakeup interrupt function by setting the EVWUPIEN bit in the EXTIWAKUPCR register and the EXTI controller will then assert an interrupt when the wakeup event occurs EVWUPIEN EVWUP interrupt N...

Page 151: ... the DBnCNT field in the EXTICFGRn so as to select an appropriate debounce time for specific applications The interrupt signal will however be delayed due to the de bounce function When the device is woken up from the power saving mode by an external interrupt an interrupt request will be generated by the EXTI wakeup flag After the device has been woken up and the clock has recovered the EXTI wake...

Page 152: ...FGR8 0x020 EXTI Interrupt 8 Configuration Register 0x0000_0000 EXTICFGR9 0x024 EXTI Interrupt 9 Configuration Register 0x0000_0000 EXTICFGR10 0x028 EXTI Interrupt 10 Configuration Register 0x0000_0000 EXTICFGR11 0x02C EXTI Interrupt 11 Configuration Register 0x0000_0000 EXTICFGR12 0x030 EXTI Interrupt 12 Configuration Register 0x0000_0000 EXTICFGR13 0x034 EXTI Interrupt 13 Configuration Register 0...

Page 153: ...8 DBnCNT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 DBnCNT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 DBnEN EXTIn De bounce Circuit Enable Bit n 0 15 0 De bounce circuit is disabled 1 De bounce circuit is enabled 30 28 SRCnTYPE EXTIn Interrupt Source Trigger Type n 0 15 SRCnTYPE 2 0 Interrupt Source Type 0 0 0 Low level Sensitive 0 0 1 Hig...

Page 154: ...eserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI7EN EXTI6EN EXTI5EN EXTI4EN EXTI3EN EXTI2EN EXTI1EN EXTI0EN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 EXTInEN EXTIn Interrupt Enable Bit...

Page 155: ... 13 12 11 10 9 8 EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 7 6 5 4 3 2 1 0 EXTI7EDF EXTI6EDF EXTI5EDF EXTI4EDF EXTI3EDF EXTI2EDF EXTI1EDF EXTI0EDF Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 Bits Field Descriptions 15 0 EXTInEDF EXTIn Edge Detection Flag n 0 15 0 No edge is detected 1 Positive or negative...

Page 156: ...e Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 7 6 5 4 3 2 1 0 EXTI7EDS EXTI6EDS EXTI5EDS EXTI4EDS EXTI3EDS EXTI2EDS EXTI1EDS EXTI0EDS Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 Bits Field Descriptions 15 0 EXTInEDS EXTIn Edge Detection...

Page 157: ...erved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15SC EXTI14SC EXTI13SC EXTI12SC EXTI11SC EXTI10SC EXTI9SC EXTI8SC Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI7SC EXTI6SC EXTI5SC EXTI4SC EXTI3SC EXTI2SC EXTI1SC EXTI0SC Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 EXTInSC EXTIn Software Set Command n...

Page 158: ...7 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI7WEN EXTI6WEN EXTI5WEN EXTI4WEN EXTI3WEN EXTI2WEN EXTI1WEN EXTI0WEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 EVWUPIEN EXTI Event Wakeup Interrupt Enable Bit 0 Disable ...

Page 159: ...4 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 EXTI7WPOL EXTI6WPOL EXTI5WPOL EXTI4WPOL EXTI3WPOL EXTI2WPOL EXTI1WPOL EXTI0WPOL Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0...

Page 160: ...rved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 EXTI15WFL EXTI14WFL EXTI13WFL EXTI12WFL EXTI11WFL EXTI10WFL EXTI9WFL EXIT8WFL Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 7 6 5 4 3 2 1 0 EXTI7WFL EXTI6WFL EXTI5WFL EXTI4WFL EXTI3WFL EXTI2WFL EXTI1WFL EXTI0WFL Type Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 Bits Field Descriptions 15 0 EXTInWFL EXTIn Wakeup...

Page 161: ...l An interrupt will then be generated to inform that the input voltage is higher or lower than the set thresholds There are three conversion modes to convert an analog signal to digital data The A D conversion can be operated in one shot continuous and discontinuous conversion mode A 16 bit data register is provided to store the data after conversion Analog Watchdog High Threshold 12 bits Low Thre...

Page 162: ...and dedicated data registers for conversion result Three conversion modes One shot conversion mode Continuous conversion mode Discontinuous conversion mode Analog watchdog for predefined voltage range monitor Lower upper threshold register Interrupt generation Various trigger start sources for conversion modes Software trigger EXTI External interrupt input pin MCTM trigger GPTM trigger PWM0 PWM1 t...

Page 163: ...process will reset the current conversion after which a new start pulse is required to restart a new conversion Conversion Mode The A D has three operating conversion modes The conversion modes are One Shot Conversion Mode Continuous Conversion Mode and Discontinuous Conversion mode Details are provided later One Shot Conversion Mode In one shot conversion mode the ADC will perform conversion cycl...

Page 164: ... Continuous Conversion Mode which can be started by a software trigger an external EXTI event or a Timer event determined by the Trigger Control Register ADCTCR and the Trigger Source Register ADCTSR After conversion The converted data will be stored in the 16 bit ADCDRy y 0 7 registers The ADC regular group and high priority group cycle end of conversion event raw status flag ADIRAWC in the ADCIR...

Page 165: ...After n conversions have completed the regular subgroup EOC interrupt raw flag ADIRAWG in the ADCIRAW register will be asserted The A D converter will now not continue to perform the next n conversions until the next trigger event occurs The conversion cycle will end after all the group channels of which the total number is defined by the ADSEQL 2 0 bits in the ADCCR register have finished their c...

Page 166: ...R register for the group channel when the software trigger enable bit ADSW in the ADCTCR register is set to 1 After the A D converter starts converting the analog data the corresponding enable bit ADSC will be cleared to 0 automatically The A D converter can also be triggered to start a group conversion by a Timer event The Timer events include a PWM master trigger output MTO four PWM channel outp...

Page 167: ...ADCDR Register Data Format Right aligned 0_0_0_0_d11_d10_d9_d8_d7_d6_d5_d4_d3_d2_d1_d0 Analog Watchdog The A D converter includes a watchdog function to monitor the converted data There are two kinds of thresholds for the watchdog monitor function known as the watchdog lower threshold and watchdog upper threshold which are specified by the ADLT bit field and ADUT bit field in the ADCTR register re...

Page 168: ...flag named as ADVLDn will be changed from low to high The converted data should be read by the application program after which the data valid flag ADVLDn will be automatically changed from high to low Otherwise a data overwrite event will occur and the data overwrite interrupt raw flag ADIRAWO bit in the ADCIRAW register will be asserted When the related data overwrite raw flag is asserted the dat...

Page 169: ...ster 1 0x0000_0000 ADCDR2 0x038 ADC Conversion Data Register 2 0x0000_0000 ADCDR3 0x03C ADC Conversion Data Register 3 0x0000_0000 ADCDR4 0x040 ADC Conversion Data Register 4 0x0000_0000 ADCDR5 0x044 ADC Conversion Data Register 5 0x0000_0000 ADCDR6 0x048 ADC Conversion Data Register 6 0x0000_0000 ADCDR7 0x04C ADC Conversion Data Register 7 0x0000_0000 ADCTCR 0x070 ADC Trigger Control Register 0x0...

Page 170: ... 8 Reserved ADSEQL Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 ADCEN ADCRST Reserved ADMODE Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 18 16 ADSUBL ADC Conversion Subgroup Length The ADSUBL field specifies the conversion channel length of each subgroup for regular discontinuous mode Subgroup length ADSUBL 2 0 1 If the sequence length ADSEQL 2 0 1 is not a multiple of the subgroup length ...

Page 171: ...uted on the specific channels for the whole conversion sequence once 01 Reserved 10 Continuous mode After a start trigger the conversion will be executed on the specific channels for the whole sequence continuously until conversion mode is changed 11 Discontinuous mode After a start trigger the conversion will be executed on the current subgroup When the last subgroup is finished the conversion wi...

Page 172: ...RW 0 7 6 5 4 3 2 1 0 Reserved ADSEQ0 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 28 24 ADSEQ3 ADC Conversion Sequence Select 3 Select ADC input channel for the 3rd ADC conversion sequence 0x00 ADC_IN0 0x01 ADC_IN1 0x02 ADC_IN2 0x03 ADC_IN3 0x04 ADC_IN4 0x05 ADC_IN5 0x06 ADC_IN6 0x07 ADC_IN7 0x08 ADC_IN8 0x09 ADC_IN9 0x0A ADC_IN10 0x0B ADC_IN11 0x0C Analog ground VSSA VREF 0x0D Anal...

Page 173: ... 7 6 5 4 3 2 1 0 Reserved ADSEQ4 Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 28 24 ADSEQ7 ADC Regular Conversion Sequence Select 7 Select ADC input channel for the 7th ADC conversion sequence 0x00 ADC_IN0 0x01 ADC_IN1 0x02 ADC_IN2 0x03 ADC_IN3 0x04 ADC_IN4 0x05 ADC_IN5 0x06 ADC_IN6 0x07 ADC_IN7 0x08 ADC_IN8 0x09 ADC_IN9 0x0A ADC_IN10 0x0B ADC_IN11 0x0C Analog ground VSSA VREF 0x0D ...

Page 174: ... D converter input channel sampling time Offset 0x020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 ADST Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 ADST ADC Input Channel Sampling Time Sampling time ADST 7 0 1 5 CK_ADC clocks ...

Page 175: ... 0x0000_0000 31 30 29 28 27 26 25 24 ADVLDy Reserved Type Reset RC 0 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 ADDy Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 ADDy Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 31 ADVLDy ADC Conversion Data of Sequence Order No y Valid Bit y 0 7 0 Data are invalid or have been read 1 New d...

Page 176: ...RW 0 Bits Field Descriptions 3 TM1 ADC Conversion BFTM or PWM Event Trigger enable control 0 Disable conversion trigger by BFTM or PWM events 1 Enable conversion trigger by BFTM or PWM events 2 TM0 ADC Conversion GPTM or MCTM Event Trigger enable control 0 Disable conversion trigger by GPTM or MCTM events 1 Enable conversion trigger by GPTM or MCTM events 1 ADEXTI ADC Conversion EXTI Event Trigger...

Page 177: ...7 TM1E PWM Trigger Event Selection of ADC Conversion 000 PWM MTO event 001 PWM CH0O event 010 PWM CH1O event 011 PWM CH2O event 100 PWM CH3O event Others Reserved Should not be used to avoid unpredictable results 26 24 TM0E GPTM or MCTM Trigger Event Selection of ADC Conversion 000 GPTM or MCTM MTO event 001 GPTM or MCTM CH0O event 010 GPTM or MCTM CH1O event 011 GPTM or MCTM CH2O event 100 GPTM o...

Page 178: ...f the ADC watchdog function Offset 0x078 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved ADUCH Type Reset RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 Reserved ADLCH Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 Reserved ADWCH Type Reset RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved ADWALL ADWUE ADWLE Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 27 24 ADUCH Upper Threshold Chann...

Page 179: ...fined memory location in the corresponding ISR Otherwise the ADLCH field will be changed if another input channel converted data is lower than the lower threshold 11 8 ADWCH ADC Watchdog Specific Channel Selection 0000 ADC_IN0 is monitored 0001 ADC_IN1 is monitored 1011 ADC_IN11 is monitored Others Reserved 2 ADWALL ADC Watchdog Specific All Channel Setting 0 Only the channel which specified by th...

Page 180: ...ed ADUT Type Reset RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 ADUT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved ADLT Type Reset RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 ADLT Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 27 16 ADUT ADC Watchdog Upper Threshold Value Specify the upper threshold for the ADC watchdog monitor function 11 0 A...

Page 181: ... ADC data register overwrite interrupt is enabled 17 ADIEU ADC Watchdog Upper Threshold Interrupt enable 0 ADC watchdog upper threshold interrupt is disabled 1 ADC watchdog upper threshold interrupt is enabled 16 ADIEL ADC Watchdog Lower Threshold Interrupt enable 0 ADC watchdog lower threshold interrupt is disabled 1 ADC watchdog lower threshold interrupt is enabled 2 ADIEC ADC Cycle EOC Interrup...

Page 182: ...verwrite interrupt occurs 17 ADIRAWU ADC Watchdog Upper Threshold Interrupt Raw Status 0 ADC watchdog upper threshold interrupt does not occur 1 ADC watchdog upper threshold interrupt occurs 16 ADIRAWL ADC Watchdog Lower Threshold Interrupt Raw Status 0 ADC watchdog lower threshold interrupt does not occur 1 ADC watchdog lower threshold interrupt occurs 2 ADIRAWC ADC Cycle EOC Interrupt Raw Status...

Page 183: ...old interrupt does not occur or watchdog upper threshold interrupt is disabled 1 ADC watchdog upper threshold interrupt occurs and watchdog upper threshold interrupt is enabled 16 ADISRL ADC Watchdog Lower Threshold Interrupt Status 0 ADC watchdog lower threshold interrupt does not occur or watchdog lower threshold interrupt is disabled 1 ADC watchdog lower threshold interrupt occurs and watchdog ...

Page 184: ...13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved ADICLRC ADICLRG ADICLRS Type Reset WO 0 WO 0 WO 0 Bits Field Descriptions 24 ADICLRO ADC Data Register Overwrite Interrupt Status Clear Bit 0 No effect 1 Clear ADISRO and ADIRAWO bits 17 ADICLRU ADC Watchdog Upper Threshold Interrupt Status Clear Bit 0 No effect 1 Clear ADISRU and ADIRAWU bits 16 ADICLRL ADC Watchdog Lower Threshold Inte...

Page 185: ...d Register CRR Output Control Output Control Output Control Output Control GT_CH0O GT_CH1O GT_CH2O GT_CH3O TI1 TI2 TI3 PSC PRESCALER Input Filter Polarity Selection Edge Detection Edge Detector ITI0 ITI1 ITI2 TI0S0ED TI0S1ED TI1S0ED TI1S1ED Input Filter Polarity Selection Edge Detection Input Filter Polarity Selection Edge Detection TI2S2ED TI2S3ED TI3S2ED TI3S3ED TRCED STIED TI0S0ED TI1S1ED TI0BE...

Page 186: ...ter counts continuously from 0 to the counter reload value which is defined in the CRR register in a count up direction Once the counter reaches the counter reload value the Timer Module generates an overflow event and the counter restarts to count once again from 0 This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be set to 0 for the up counting mod...

Page 187: ...ce again from the counter reload value This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be set to 1 for the down counting mode When the update event is set by the UEVG bit in the EVGR register the counter value will also be initialized to the counter reload value CK_PSC CNT_EN 2 1 0 CK_CNT 3 F5 CNTR CRR Shadow Register CRR 36 F5 36 0 1 0 1 PSCR PSCR...

Page 188: ...ster is read only and indicates the counting direction when in the center aligned mode The counting direction is updated by hardware automatically Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center aligned counting mode The UEVIF bit in the INTSR register will be set to 1 when an overflow or unde...

Page 189: ... pulse to drive the counter prescaler The counting direction bit DIR is modified by hardware automatically at each transition on the input source signal The input source signal can be derived from the GT_CH0 pin only the GT_CH1 pin only or both GT_CH0 and GT_CH1 pins STIED The counter prescaler can count during each rising edge of the STI signal This mode can be selected by setting the SMSEL field...

Page 190: ...me GPTM functions which are triggered by a trigger signal rising edge Trigger Controller Block Edge Trigger Mux Level Trigger Mux Edge Detection ITI0 ITI1 ITI2 ITI0ED ITI1ED ITI2ED STIED TRCED TI0S0ED TI1S1ED TRSEL 2 0 TRSEL 3 0 1 0 Edge Trigger Mux TI0BED ITI0ED ITI1ED ITI2ED STI TRSEL 2 0 TRSEL 3 0 1 0 S W Set UEVG Bit TI0S0 TI1S1 ITI0 ITI1 ITI2 Level Trigger Source Internal ITIx Channel input T...

Page 191: ...update event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set Then the counter and prescaler will be reinitialized Although the UEVG bit is set to 1 by hardware the update event does not really occur It depends upon whether the update event disable control bit UEVDIS is set to 1 or not If the UEVDIS is set to 1 to disable the...

Page 192: ...ity 0 STI source signal Sync polarity 1 Figure 38 GPTM in Pause Mode Trigger Mode After the counter is disabled to count the counter can resume counting when an STI rising edge signal occurs When an STI rising edge occurs the counter will start to count from the current value in the counter Note that if the STI signal is selected to be derived from the UEVG bit software trigger the counter will no...

Page 193: ...TM or MCTM if exists which is configured in the Slave Mode GPTMn Master MTO ITI GPTMm MCTMm Slave MMSEL SMSEL TSE TRSEL Figure 40 Master GPTMn and Slave GPTMm MCTMm Connection The Master Mode Selection bits MMSEL in the MDCFR register are used to select the MTO source for synchronizing another slave GPTM or MCTM if exists Channel 0 Capture Compare event MTO UEVG bit Counter enable signal Update Ev...

Page 194: ...e input capture mode the counter value is captured into the CHxCCR shadow register first and then transferred into the CHxCCR preload register when the capture event occurs When used in the compare match output mode the contents of the CHxCCR preload register is copied into the associated shadow register the counter value is then compared with the register value CHxCCR Preload Register CHxCCR Shad...

Page 195: ...ister CHxCCR when an effective input signal transition occurs Once the capture event occurs the CHxCCIF flag in the INTSR register is set accordingly If the CHxCCIF bit is already set i e the flag has not yet been cleared by software and another capture event on this channel occurs the corresponding channel Over Capture flag named CHxOCF will be set 25 26 27 28 29 30 31 32 33 34 35 0 26 32 CNTR CH...

Page 196: ...the capture channel 1 CH1CCS 0x2 to select the TI0 signal as the capture input Configure the CH1P bit to 1 to choose the falling edge of the TI0 input as the active polarity Configure the TRSEL bits to 0x1 to select TI0S0 as the trigger input Configure the Slave controller to operate in the Restart mode by setting the SMSEL field in the MDCFR register to 0x4 Enable the input capture mode by settin...

Page 197: ...Then the channel polarity and the edge detection block can generate a TIxS0ED or TIxS1ED signal for the input capture function The effective input event number can be set by the channel capture input source prescaler setting field CHxPSC Filter TI0FP TI0FN TI0F GT_CH0 fsampling CH0P Filter TI1FP TI1FN TI1F CH1P GT_CH1 TI0S0 TI1S0 TI0S1 TI1S1 TRCED CH0PRESCALER CH1PRESCALER TI0S0ED CH0PSC CH1PSC CH...

Page 198: ...n TI3S2ED TI2S3ED TI3S3ED fCLKIN fsampling fsampling TI2 TI3 Figure 46 Channel 2 and Channel 3 Input Stages Digital Filter The digital filters are embedded in the input stage for the GT_CH0 GT_CH3 pins respectively The digital filter in the GPTM is an N event counter where N refers to how many valid transitions are necessary to output a filtered signal The N value can be 0 2 4 5 6 or 8 according t...

Page 199: ...e Quadrature decoder can be regarded as an external clock with a directional selection This means that the counter counts continuously in the interval between 0 and the counter reload value Therefore users must configure the CRR register before the counter starts to count Filter TI0FP TI0FN TI0F GT_CH0 fsampling CH0P Filter TI1FP TI1FN TI1F CH1P GT_CH1 TI0S0 TI1S0 TI0S1 TI1S1 TRCED CH0PRESCALER CH...

Page 200: ...g Counting on TI0 only SMSEL 0x1 TI1S1 High Down Up TI1S1 Low Up Down Counting on TI1 only SMSEL 0x2 TI0S0 High Up Down TI0S0 Low Down Up Counting on TI0 and TI1 SMSEL 0x3 TI1S1 High Down Up X X TI1S1 Low Up Down X X TI0S0 High X X Up Down TI0S0 Low X X Down Up Note no counting X impossible TI0 TI1 Up Down Quadrature Decoder Counting on Both TI0 TI1 CH0P 0 CH1P 0 Figure 49 Both TI0 and TI1 Quadrat...

Page 201: ...l types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register In addition to the low high and toggle CHxOREF output types there are also PWM mode 1 and PWM mode 2 outputs In these modes the CHxOREF signal level is changed according to the count direction and the relationship between the counter value and the CHxCCR content Th...

Page 202: ... Update Event Time Output toggle preload disable CHxCCR New value 3 Update CHxCCR value 1 2 3 Figure 51 Toggle Mode Channel Output Reference Signal CHxPRE 0 Counter Value CRR CHxOM 0x3 CHxPRE 1 CHxCCR CHxCCR New value 1 CHxCCR New value 2 Time Output toggle preload enable CHxCCR New value 3 Update CHxCCR value 1 2 3 TME CHxOREF UEV Update Event Figure 52 Toggle Mode Channel Output Reference Signal...

Page 203: ...Value 100 0 CHxOM 0x7 CHxCCR CRR CHxOREF CHxCCIF CHxCCIF CHxOREF CHxCCR 0x0000 CRR Counter Value Figure 53 PWM Mode Channel Output Reference Signal and Counter in Up counting Mode Counter Value CRR CHxCCR CHxOREF CHxOM 0x6 CHxOM 0x7 CHxOREF 100 CRR CHxCCR Counter Value CHxOREF CHxCCIF CHxCCIF Figure 54 PWM Mode Channel Output Reference Signal and Counter in Down counting Mode ...

Page 204: ...1 HT32F50241 13 General Purpose Timer GPTM Up counting Down counting CRR 5 CHxCCR 3 CMSEL 0x1 CHxCCIF CHxCCR 4 CHxCCIF CHxCCR 5 CHxCCR 0 CHxCCIF CHxCCIF 100 0 0 1 2 3 4 5 4 3 2 1 0 1 Figure 55 PWM Mode Channel Output Reference Signal and Counter in Centre aligned Mode ...

Page 205: ...FR register can determine whether the update event occurs or not When the update event occurs the corresponding update event interrupt will be generated depending upon whether the update event interrupt generation function is enabled or not by configuring the UGDIS bit in the CNTCFR register For more detail description refer to the UEVDIS and UGDIS bit definition in the CNTCFR register UEVDIS UEV ...

Page 206: ... keep the TME bit at a high state until the update event occurs or the TME bit is written to 0 by software If the TME bit is cleared to 0 using software the counter will be stopped and its value held If the TME bit is automatically cleared to 0 by a hardware update event the counter will be reinitialized Trigger by S W Trigger by STI Cleared by Update Event Flag is set by compare match and cleared...

Page 207: ...CFR register After an STI rising edge trigger occurs in the single pulse mode the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigger source i...

Page 208: ...er is into counting down stage the PWM uses the value in CHxACR as down count compare value The Figure 59 is shown as an example for asymmetric PWM mode in center aligned counting mode Note Asymmetric PWM mode can only be operated in center aligned counting mode 2 3 4 5 6 7 0 1 8 5 4 3 2 1 0 7 6 2 3 4 5 6 7 1 8 5 4 3 2 1 0 7 6 2 3 4 5 6 7 1 8 5 4 3 2 1 7 6 CNTR CHxOREF CHxOREF CHxOREF CHxOREF PWM ...

Page 209: ...and slave modes Using One Timer to Enable Disable Another Timer Start or Stop Counting Configure GPTM as the master mode to send its channel 0 Output Reference signal CH0OREF as a trigger output MMSEL 0x4 Configure GPTM CH0OREF waveform Configure MCTM to receive its input trigger source from the GPTM trigger output TRSEL 0xA Configure MCTM to operate in the pause mode SMSEL 0x5 Enable MCTM by writ...

Page 210: ...t UEV as the trigger output MMSEL 0x2 Configure the GPTM period by setting the CRR register Configure MCTM to get the input trigger source from the GPTM trigger output TRSEL 0xA Configure MCTM to be in the slave trigger mode SMSEL 0x6 Start GPTM by writing 1 to the TME bit 14 15 00 01 02 FB FC FA 03 13 fCLKIN GPTM CNTR MCTM CNTR Software clearing MCTM TME bit MCTM TEVIF FD GPTM UEVIF Figure 61 Tri...

Page 211: ...the slave trigger mode SMSEL 0x6 Enable the GPTM master timer synchronization function by setting the TSE bit in the MDCFR register to 1 to synchronize the slave timer Configure MCTM to receive its input trigger source from the GPTM trigger output TRSEL 0xA Configure MCTM to be in the slave trigger mode SMSEL 0x6 TI0 TI0FP fDTS fCLKIN TI0S0ED GPTM TME bit GPTM TEVIF TSE 1 Delay GPTM CK_PSC MCTM TM...

Page 212: ...0x040 Channel 0 Output Configuration Register 0x0000_0000 CH1OCFR 0x044 Channel 1 Output Configuration Register 0x0000_0000 CH2OCFR 0x048 Channel 2 Output Configuration Register 0x0000_0000 CH3OCFR 0x04C Channel 3 Output Configuration Register 0x0000_0000 CHCTR 0x050 Channel Control Register 0x0000_0000 CHPOLR 0x054 Channel Polarity Configuration Register 0x0000_0000 DICTR 0x074 Timer Interrupt Co...

Page 213: ...s mode Counting direction is defined by the DIR bit 01 Center aligned mode 1 The counter counts up and down alternatively The compare match interrupt flag is set during the count down period 10 Center aligned mode 2 The counter counts up and down alternatively The compare match interrupt flag is set during the count up period 11 Center aligned mode 3 The counter counts up and down alternatively Th...

Page 214: ...received from the slave mode Timer Mode Configuration Register MDCFR This register specifies the GPTM master and slave mode selection and single pulse mode Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved SPMSET Type Reset RW 0 23 22 21 20 19 18 17 16 Reserved MMSEL Type Reset RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved SMSEL Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserve...

Page 215: ... trigger output 010 Update Mode The update event is used as the trigger output according to one of the following cases when the UEVDIS bit is cleared to 0 1 Counter overflow underflow 2 Software setting UEVG 3 Slave trigger input when used in slave restart mode 011 Capture Compare Mode When a Channel 0 capture or compare match event occurs it will generate a positive pulse used as the master trigg...

Page 216: ...d TI1 signals to drive the counter prescaler A transition of one channel edge is used in the quadrature decoder mode 3 depending upon the other channel level 100 Restart Mode The counter value restarts from 0 or the CRR shadow register value depending upon the counter mode on the rising edge of the STI signal The registers will also be updated 101 Pause Mode The counter starts to count when the se...

Page 217: ...tions 3 0 TRSEL Trigger Source Selection These bits are used to select the trigger input STI for counter synchronization 0000 Software Trigger by setting the UEVG bit 0001 Filtered input of channel 0 TI0S0 0010 Filtered input of channel 1 TI1S1 0011 Reserved 1000 Channel 0 Edge Detector TI0BED 1001 Internal Timing Module Trigger 0 ITI0 1010 Internal Timing Module Trigger 1 ITI1 1011 Internal Timin...

Page 218: ...eserved CRBE TME Type Reset RW 0 RW 0 Bits Field Descriptions 1 CRBE Counter Reload register Buffer Enable 0 Counter reload register can be updated immediately 1 Counter reload register can not be updated until the update event occurs 0 TME Timer Enable bit 0 GPTM off 1 GPTM on GPTM functions normally When the TME bit is cleared to 0 the counter is stopped and the GPTM consumes no power in any ope...

Page 219: ...hannel 0 Capture Input Source Prescaler Setting These bits define the effective events of the channel 0 capture input Note that the prescaler is reset once the Channel 0 Capture Compare Enable bit CH0E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 0 capture input signal is chosen for each active event 01 Channel 0 Capture input signal is chosen for every 2 eve...

Page 220: ...1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Channel 1 Input Configuration Register CH1ICFR This register specifies the channel 1 input mode configuration Offset 0x024 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CH1PSC CH1CCS Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved TI1F Type ...

Page 221: ... is cleared to 0 3 0 TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divided ratio used to sample the TI1 signal The Digital filter in the GPTM is an N event counter where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fSAMPLING fCLKIN N 2 0010 fSAMPLING fCLKIN N 4 0011 fSAMPLING ...

Page 222: ...ure input Note that the prescaler is reset once the Channel 2 Capture Compare Enable bit CH2E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 2 capture input signal is chosen for each active event 01 Channel 2 Capture input signal is chosen for every 2 events 10 Channel 2 Capture input signal is chosen for every 4 events 11 Channel 2 Capture input signal is chos...

Page 223: ...1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Channel 3 Input Configuration Register CH3ICFR This register specifies the channel 3 input mode configuration Offset 0x02C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CH3PSC CH3CCS Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved TI3F Type ...

Page 224: ...er where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fSAMPLING fCLKIN N 2 0010 fSAMPLING fCLKIN N 4 0011 fSAMPLING fCLKIN N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 ...

Page 225: ...eference signal CH0OREF 0000 No Change 0001 Output 0 on compare match 0010 Output 1 on compare match 0011 Output toggles on compare match 0100 Force inactive CH0OREF is forced to 0 0101 Force active CH0OREF is forced to 1 0110 PWM mode 1 During up counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level During down counting channel 0 has an inactive level when CNT...

Page 226: ... Active Mode is enabled The CH1OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH1IMAE bit is available only if the channel 1 is configured to be operated in the PWM mode 1...

Page 227: ...l 0111 PWM mode 2 During up counting channel 1 has an inactive level when CNTR CH1CCR or otherwise has an active level During down counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level During down counting channel 1 has an inactive lev...

Page 228: ... Active Mode is enabled The CH2OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH2IMAE bit is available only if the channel 2 is configured to be operated in the PWM mode 1...

Page 229: ...l 0111 PWM mode 2 During up counting channel 2 has an inactive level when CNTR CH2CCR or otherwise has an active level During down counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level During down counting channel 2 has an inactive lev...

Page 230: ... Active Mode is enabled The CH3OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH3IMAE bit is available only if the channel 3 is configured to be operated in the PWM mode 1...

Page 231: ...l 0111 PWM mode 2 During up counting channel 3 has an inactive level when CNTR CH3CCR or otherwise has an active level During down counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level During down counting channel 3 has an inactive lev...

Page 232: ...d on the corresponding output pin 4 CH2E Channel 2 Capture Compare Enable Channel 2 is configured as an input CH2CCS 0x1 0x2 0x3 0 Input Capture Mode is disabled 1 Input Capture Mode is enabled Channel 2 is configured as an output CH2CCS 0x0 0 Off Channel 2 output signal CH2O is not active 1 On Channel 2 output signal CH2O generated on the corresponding output pin 2 CH1E Channel 1 Capture Compare ...

Page 233: ... active high 1 Channel 3 Output is active low 4 CH2P Channel 2 Capture Compare Polarity When Channel 2 is configured as an input CH2CCS 0x1 0x2 0x3 0 Capture event occurs on a Channel 2 rising edge 1 Capture event occurs on a Channel 2 falling edge When Channel 2 is configured as an output CH2CCS 0x0 0 Channel 2 Output is active high 1 Channel 2 Output is active low 2 CH1P Channel 1 Capture Compar...

Page 234: ...riptions 10 TEVIE Trigger event Interrupt Enable 0 Trigger event interrupt is disabled 1 Trigger event interrupt is enabled 8 UEVIE Update event Interrupt Enable 0 Update event interrupt is disabled 1 Update event interrupt is enabled 3 CH3CCIE Channel 3 Capture Compare Interrupt Enable 0 Channel 3 interrupt is disabled 1 Channel 3 interrupt is enabled 2 CH2CCIE Channel 2 Capture Compare Interrupt...

Page 235: ...e returns to 0 or the CRR preload value depending on the counter mode in which the current timer is being used An update operation of any related registers will also be performed For more detail descriptions refer to the corresponding section 3 CH3CCG Channel 3 Capture Compare Generation A Channel 3 capture compare event can be generated by setting this bit It is cleared by hardware automatically ...

Page 236: ... by hardware automatically 0 No action 1 Capture compare event is generated on channel 0 If Channel 0 is configured as an input the counter value is captured into the CH0CCR register and then the CH0CCIF bit is set If Channel 0 is configured as an output the CH0CCIF bit is set Timer Interrupt Status Register INTSR This register stores the timer interrupt status Offset 0x07C Reset value 0x0000_0000...

Page 237: ... set and it is not cleared yet by software 4 CH0OCF Channel 0 Over Capture Flag This flag is set by hardware and cleared by software 0 No over capture event is detected 1 Capture event occurs again when the CH0CCIFbit is already set and it is not yet cleared by software 3 CH3CCIF Channel 3 Capture Compare Interrupt Flag Channel 3 is configured as an output 0 No match event occurs 1 The contents of...

Page 238: ...ompare Interrupt Flag Channel 0 is configured as an output 0 No match event occurs 1 The contents of the counter CNTR have matched the content of the CH0CCR register This flag is set by hardware when the counter value matches the CH0CCR value except in the center aligned mode It is cleared by software Channel 0 is configured as an input 0 No input capture occurs 1 Input capture occurs This bit is ...

Page 239: ... 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PSCV Prescaler Value These bits are used to specify the prescaler value to generate the counter clock frequency fCK_CNT fCK_CNT fCK_PSC...

Page 240: ...ffset 0x088 Reset value 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CRV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 7 6 5 4 3 2 1 0 CRV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 15 0 CRV Counter Reload Value The CRV is the reload value which is loaded into the actual counter regist...

Page 241: ...ed Type Reset 15 14 13 12 11 10 9 8 CH0CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH0CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH0CCV Channel 0 Capture Compare Value When Channel 0 is configured as an output The CH0CCR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal...

Page 242: ...ed Type Reset 15 14 13 12 11 10 9 8 CH1CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH1CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH1CCV Channel 1 Capture Compare Value When Channel 1 is configured as an output The CH1CCR value is compared with the counter value and the comparison result is used to trigger the CH1OREF output signal...

Page 243: ...ed Type Reset 15 14 13 12 11 10 9 8 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH2CCV Channel 2 Capture Compare Value When Channel 2 is configured as an output The CH2CCR value is compared with the counter value and the comparison result is used to trigger the CH2OREF output signal...

Page 244: ...ed Type Reset 15 14 13 12 11 10 9 8 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH3CCV Channel 3 Capture Compare Value When Channel 3 is configured as an output The CH3CCR value is compared with the counter value and the comparison result is used to trigger the CH3OREF output signal...

Page 245: ...lue When channel 0 is configured as asymmetric PWM mode and the counter is counting down the value written is this register will be compared to the counter Channel 1 Asymmetric Compare Register CH1ACR This register specifies the timer channel 1 asymmetric compare value Offset 0x0A4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14...

Page 246: ...lue When channel 2 is configured as asymmetric PWM mode and the counter is counting down the value written is this register will be compared to the counter Channel 3 Asymmetric Compare Register CH3ACR This register specifies the timer channel 3 asymmetric compare value Offset 0x0AC Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14...

Page 247: ...e generation or PWM output CH1 Compare Register CH1CR CH2 Compare Register CH2CR CH3 Compare Register CH3CR TM_CNT CH0 Compare Register CH0CR Reload Register CRR Output Control Output Control Output Control Output Control PWM_CH0 PWM_CH1 PWM_CH2 PWM_CH3 PSC PRESCALER Edge Detector ITI0 ITI1 ITI2 STIED Colck Controller fCLKIN CK_CNT CK_PSC Slave Controller STI CH0OREF CH1OREF CH2OREF CH3OREF Restar...

Page 248: ...l Descriptions Counter Mode Up Counting In this mode the counter counts continuously from 0 to the counter reload value which is defined in the CRR register in a count up direction Once the counter reaches the counter reload value the Timer Module generates an overflow event and the counter restarts to count once again from 0 This action will continue repeatedly The counting direction bit DIR in t...

Page 249: ...ce again from the counter reload value This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be set to 1 for the down counting mode When the update event is set by the UEVG bit in the EVGR register the counter value will also be initialized to the counter reload value CK_PSC CNT_EN 2 1 0 CK_CNT 3 F5 CNTR CRR Shadow Register CRR 36 F5 36 0 1 0 1 PSCR PSCR...

Page 250: ...ister is read only and indicates the counting direction when in the center align mode The counting direction is updated by hardware automatically Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center aligned counting mode The UEVIF bit in the INTSR register can be set to 1 when an overflow or underf...

Page 251: ...event counter The input event known as STI here can be selected by setting the TRSEL field to an available value except the value of 0x0 When the STI signal is selected as the clock source the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescaler It is important to note that if the TRSEL field is set to 0x0 to select the sof...

Page 252: ...edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some PWM functions which are triggered by a trigger signal rising edge STIED TRSEL 3 0 Edge Trigger Mux ITI0ED ITI1ED ITI2ED STI TRSEL 3 0 ITI0 ITI1 ITI2 Reserved 0000 1001 1010 1011 others 0000 1001 1010 1011 others Reserved Level Trigger Mux Reserved S W Set UEVG Bit Trigger Controller Block Edge...

Page 253: ...date event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set Then the counter and prescaler will be reinitialized Although the UEVG bit is set to 1 by hardware the update event does not really occur It depends upon whether the update event disable control bit UEVDIS is set to 1 or not If the UEVDIS is set to 1 to disable the u...

Page 254: ... 1 Figure 71 PWM in Pause Mode Trigger Mode After the counter is disabled to count the counter can resume counting when an STI rising edge signal occurs When an STI rising edge occurs the counter will start to count from the current value in the counter Note that if the STI signal is selected to be derived from the UEVG bit software trigger the counter will not resume counting When software trigge...

Page 255: ...r or drive another PWM or TM if exists which is configured in the Slave Mode PWMn Master MTO ITI PWMm TMm Slave MMSEL SMSEL TSE TRSEL Figure 73 Master PWMn and Slave PWMm TMm Connection The Master Mode Selection bits MMSEL in the MDCFR register are used to select the MTO source for synchronizing another slave PWM or TM if exists MTO UEVG bit Counter enable signal Update Event CH0OREF CH1OREF CH2OR...

Page 256: ...egister is copied into the associated shadow register the counter value is then compared with the register value CHxCR Preload Register CHxCR Shadow Register APB Bus Interface Compare Controller Compare Transfer CHxPRE Write CHxCR Update Event CNTR Figure 75 Compare Block Diagram Output Stage The PWM has four channels for compare match single pulse or PWM output function The channel output PWM_CHx...

Page 257: ...irection and the relationship between the counter value and the CHxCR content There are also two modes which will force the output into an inactive or active state irrespective of the CHxCR content or counter values With regard to a more detailed description refer to the relative bit definition The accompanying Table 30 shows a summary of the output type setup Table 30 Compare Match Output Setup C...

Page 258: ...t toggle preload enable CHxCR New value 3 Update CHxCR value 1 2 3 TME CHxOREF UEV Update Event Figure 78 Toggle Mode Channel Output Reference Signal CHxPRE 1 Counter Value CRR CHxCR CHxOREF CHxOM 0x6 CHxCIF CHxOREF Counter Value 100 0 CHxOM 0x7 CHxCR CRR CHxOREF CHxCIF CHxCIF CHxOREF CHxCR 0x0000 CRR Counter Value Figure 79 PWM Mode Channel Output Reference Signal and Counter in Up counting Mode ...

Page 259: ... CHxOREF 100 CRR CHxCR Counter Value CHxOREF CHxCIF CHxCIF Figure 80 PWM Mode Channel Output Reference Signal and Counter in Down counting Mode Up counting Down counting CRR 5 CHxCR 3 CMSEL 0x1 CHxCIF CHxCR 4 CHxCIF CHxCR 5 CHxCR 0 CHxCIF CHxCIF 100 0 0 1 2 3 4 5 4 3 2 1 0 1 Figure 81 PWM Mode Channel Output Reference Signal and Counter in Centre aligned Mode ...

Page 260: ...it definition in the CNTCFR register UEVDIS UEV Update PSCR CRR CHxCR CHxACR Shadow Registers Slave Restart mode UGDIS Counter Overflow Underflow UEVDIS UEV interrupt UEVG Slave Restart mode Update Event Management Update Event Interrupt Management UEVG Counter Overflow Underflow Figure 82 Update Event Setting Diagram Single Pulse Mode Once the timer is set to operate in the single pulse mode it i...

Page 261: ...e Event Flag is set by compare match and cleared by S W CRR CHxCR TME bit STI UEVIF CHxCIF Counter Value Flag is set by update event and cleard by S W Counter stopped and held Time Counter reinitialized Cleared by S W delay delay CHxOREF PWM1 delay delay PWM2 CHxIMAE 0 min delay CHxIMAE 1 min delay CHxOREF PWM1 PWM2 delay delay Figure 83 Single Pulse Mode ...

Page 262: ...HxOCFR register After an STI rising edge trigger occurs in the single pulse mode the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account The CHxIMAE bit is available only when the output channel is configured to operate in the PWM Mode 1 or PWM Mode 2 and the trigger sourc...

Page 263: ...REF PWM center align mode CRR 8 CR 3 ACR X PWM center align mode CRR 8 CR 5 ACR X Asymetric PWM center align mode CRR 8 CR 3 ACR 5 Asymetric PWM center align mode CRR 8 CR 5 ACR 3 CR 3 CR 5 CR 3 ACR 5 CR 5 ACR 3 Phase delay 2 CRR 8 Figure 85 Asymmetric PWM Mode versus Center aligned Counting Mode Timer Interconnection The timers can be internally connected together for timer chaining or synchroniz...

Page 264: ...timer start counting Configure PWM0 to operate in the master mode to send its Update Event UEV as the trigger output MMSEL 0x2 Configure the PWM0 period by setting the CRR register Configure PWM1 to get the input trigger source from the PWM0 trigger output TRSEL 0x9 Configure PWM1 to be in the slave trigger mode SMSEL 0x6 Start PWM0 by writing 1 to the TME bit 14 15 00 01 02 FB FC FA 03 13 fCLKIN ...

Page 265: ... the PWM0 trigger output TRSEL 0x9 Configure PWM1 to be in the slave trigger mode SMSEL 0x6 Set 1 to the PWM1 TME bit Start PWM0 by writing 1 to the TME bit fDTS fCLKIN PWM0 TME bit TSE 1 Delay PWM0 CK_PSC PWM1 TME bit PWM1 TEVIF PWM1 CK_PSC 0 1 2 3 4 PWM0 CNTR PWM1 CNTR 0 1 2 3 4 34 11 Write UEVG bit Write UEVG bit ITI 5 5 Master PWM0 Slave PWM1 Figure 88 Trigger PWM0 and PWM1 with the PWM0 Timer...

Page 266: ...uration Register 0x0000_0000 CHCTR 0x050 Channel Control Register 0x0000_0000 CHPOLR 0x054 Channel Polarity Configuration Register 0x0000_0000 DICTR 0x074 Timer Interrupt Control Register 0x0000_0000 EVGR 0x078 Timer Event Generator Register 0x0000_0000 INTSR 0x07C Timer Interrupt Status Register 0x0000_0000 CNTR 0x080 Timer Counter Register 0x0000_0000 PSCR 0x084 Timer Prescaler Register 0x0000_0...

Page 267: ...1 The counter counts up and down alternatively The compare match interrupt flag is set during the count down period 10 Center aligned mode 2 The counter counts up and down alternatively The compare match interrupt flag is set during the count up period 11 Center aligned mode 3 The counter counts up and down alternatively The compare match interrupt flag is set during the count up and count down pe...

Page 268: ...000 31 30 29 28 27 26 25 24 Reserved SPMSET Type Reset RW 0 23 22 21 20 19 18 17 16 Reserved MMSEL Type Reset RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved SMSEL Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved TSE Type Reset RW 0 Bits Field Descriptions 24 SPMSET Single Pulse Mode Setting 0 Counter counts normally irrespective of whether the update event occurred or not 1 Counter stops counting...

Page 269: ... Restart mode 001 Enable Mode The Counter Enable signal is used as the trigger output 010 Update Mode The update event is used as the trigger output according to one of the following cases when the UEVDIS bit is cleared to 0 1 Counter overflow underflow 2 Software setting UEVG 3 Slave trigger input when used in slave restart mode 011 Reserved 100 Compare Mode 0 The Channel 0 Output reference signa...

Page 270: ...use Mode The counter starts to count when the selected trigger input STI is high The counter stops counting on the instant not being reset when the STI signal changes its state to a low level Both the counter start and stop control are determined by the STI signal 110 Trigger Mode The counter starts to count from the original value in the counter on the rising edge of the selected trigger input ST...

Page 271: ...SEL Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 3 0 TRSEL Trigger Source Selection These bits are used to select the trigger input STI for counter synchronization 0000 Software Trigger by setting the UEVG bit 1001 Internal Timing Module Trigger 0 ITI0 1010 Internal Timing Module Trigger 1 ITI1 1011 Internal Timing Module Trigger 2 ITI2 Others Reserved Note These bits must be updated onl...

Page 272: ... 5 4 3 2 1 0 Reserved CRBE TME Type Reset RW 0 RW 0 Bits Field Descriptions 1 CRBE Counter Reload register Buffer Enable 0 Counter reload register can be updated immediately 1 Counter reload register can not be updated until the update event occurs 0 TME Timer Enable bit 0 PWM off 1 PWM on When the TME bit is cleared to 0 the counter is stopped and the PWM consumes no power in any operation mode e...

Page 273: ...Immediate Active Mode is enabled The CH0OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CR values The effective duration ends automatically at the next overflow or underflow event Note The CH0IMAE bit is available only if the channel 0 is configured to be operated in the PW...

Page 274: ... 0111 PWM mode 2 During up counting channel 0 is has an inactive level when CNTR CH0CR or otherwise has an active level During down counting channel 0 has an active level when CNTR CH0CR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 0 has an active level when CNTR CH0CR or otherwise has an inactive level During down counting channel 0 has an inactive leve...

Page 275: ...ediate Active Mode is enabled The CH1OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CR values The effective duration ends automatically at the next overflow or underflow event Note The CH1IMAE bit is available only if the channel 1 is configured to be operated in th...

Page 276: ...el 0111 PWM mode 2 During up counting channel 1 has an inactive level when CNTR CH1CR or otherwise has an active level During down counting channel 1 has an active level when CNTR CH1CR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 1 has an active level when CNTR CH1CR or otherwise has an inactive level During down counting channel 1 has an inactive level...

Page 277: ...ediate Active Mode is enabled The CH2OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CR values The effective duration ends automatically at the next overflow or underflow event Note The CH2IMAE bit is available only if the channel 2 is configured to be operated in th...

Page 278: ...el 0111 PWM mode 2 During up counting channel 2 has an inactive level when CNTR CH2CR or otherwise has an active level During down counting channel 2 has an active level when CNTR CH2CR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 2 has an active level when CNTR CH2CR or otherwise has an inactive level During down counting channel 2 has an inactive level...

Page 279: ...ediate Active Mode is enabled The CH3OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CR values The effective duration ends automatically at the next overflow or underflow event Note The CH3IMAE bit is available only if the channel 3 is configured to be operated in th...

Page 280: ...el 0111 PWM mode 2 During up counting channel 3 has an inactive level when CNTR CH3CR or otherwise has an active level During down counting channel 3 has an active level when CNTR CH3CR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 3 has an active level when CNTR CH3CR or otherwise has an inactive level During down counting channel 3 has an inactive level...

Page 281: ...0 Bits Field Descriptions 6 CH3E Channel 3 Compare Enable 0 Off Channel 3 output signal CH3O is not active 1 On Channel 3 output signal CH3O is generated on the corresponding output pin 4 CH2E Channel 2 Capture Compare Enable 0 Off Channel 2 output signal CH2O is not active 1 On Channel 2 output signal CH2O is generated on the corresponding output pin 2 CH1E Channel 1 Capture Compare Enable 0 Off ...

Page 282: ... 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CH3P Reserved CH2P Reserved CH1P Reserved CH0P Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 6 CH3P Channel 3 Compare Polarity 0 Channel 3 Output is active high 1 Channel 3 Output is active low 4 CH2P Channel 2 Compare Polarity 0 Channel 2 Output is active high 1 Channel 2 Output is active low 2 CH1P Channel 1 Compare Polarity 0 Chan...

Page 283: ... Bits Field Descriptions 10 TEVIE Trigger event Interrupt Enable 0 Trigger event interrupt is disabled 1 Trigger event interrupt is enabled 8 UEVIE Update event Interrupt Enable 0 Update event interrupt is disabled 1 Update event interrupt is enabled 3 CH3CIE Channel 3 Compare Interrupt Enable 0 Channel 3 interrupt is disabled 1 Channel 3 interrupt is enabled 2 CH2CIE Channel 2 Compare Interrupt E...

Page 284: ... bit It is cleared by hardware automatically 0 No action 1 Reinitialize the counter The counter value returns to 0 or the CRR preload value depending on the counter mode in which the current timer is being used An update operation of any related registers will also be performed For more detailed descriptions refer to the corresponding section 3 CH3CG Channel 3 Compare Generation A Channel 3 compar...

Page 285: ...IF CH1CIF CH0CIF Type Reset RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 10 TEVIF Trigger Event Interrupt Flag This flag is set by hardware on a trigger event and is cleared by software 0 No trigger event occurs 1 Trigger event occurs 8 UEVIF Update Event Interrupt Flag This bit is set by hardware on an update event and is cleared by software 0 No update event occurs 1 Update event occurs Note The ...

Page 286: ...ware when the counter value matches the CH1CR value except in the center aligned mode It is cleared by software 0 CH0CIF Channel 0 Compare Interrupt Flag 0 No match event occurs 1 The content of the counter CNTR has matched the content of the CH0CR register This flag is set by hardware when the counter value matches the CH0CR value except in the center aligned mode It is cleared by software Timer ...

Page 287: ...Descriptions 15 0 PSCV Prescaler Value These bits are used to specify the prescaler value to generate the counter clock frequency fCK_CNT fCK_CNT fCK_PSC PSCV 15 0 1 where the fCK_PSC is the prescaler clock source Timer Counter Reload Register CRR This register specifies the timer counter reload value Offset 0x088 Reset value 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 1...

Page 288: ...5 0 CH0CV Channel 0 Compare Value The CH0CR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal Channel 1 Compare Register CH1CR This register specifies the timer channel 1 compare value Offset 0x094 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH1CV ...

Page 289: ...ns 15 0 CH2CV Channel 2 Compare Value The CH2CR value is compared with the counter value and the comparison result is used to trigger the CH2OREF output signal Channel 3 Compare Register CH3CR This register specifies the timer channel 3 compare value Offset 0x09C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 CH...

Page 290: ...lue When channel 0 is configured as asymmetric PWM mode and the counter is counting down the value written is this register will be compared to the counter Channel 1 Asymmetric Compare Register CH1ACR This register specifies the timer channel 1 asymmetric compare value Offset 0x0A4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14...

Page 291: ...lue When channel 2 is configured as asymmetric PWM mode and the counter is counting down the value written is this register will be compared to the counter Channel 3 Asymmetric Compare Register CH3ACR This register specifies the timer channel 3 asymmetric compare value Offset 0x0A8 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14...

Page 292: ...h compare match event which is generated by the internal comparator The BFTM also supports a one shot mode which will force the counter to stop counting when a compare match event occurs BFTMCMPR Comparator BFTMCNTR 32 bit Up Counter Counter Controller BFTM APB clock EN CLR MIEN MIF To NVIC OSM Figure 89 BFTM Block Diagram Features 32 bit up counting counter Compare Match function Includes debug m...

Page 293: ... by the BFTMCMPR register When the BFTM operates in the repetitive mode and the counter reaches a value equal to the specific compare value in the BFTMCMPR register the timer will generate a compare match event signal MIF When this occurs the counter will be reset to 0 and resume its counting operation When the MIF signal is generated a BFTM compare match interrupt will also be generated periodica...

Page 294: ...ue will be reset to 0 and stop counting when the CEN bit is cleared automatically to 0 by the internal hardware when a counter compare match event occurs CMP CNT MIF CEN Time CNT value unchanged when CEN is reset By S W Cleared by hardware Cleared by software Updated by software Figure 91 BFTM One Shot Mode CMP CNT MIF CEN Time 0xFFFF_FFFF Cleared by hardware Cleared by software Updated by softwar...

Page 295: ...Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved CEN OSM MIEN Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 2 CEN BFTM Counter Enable Control 0 BFTM is disabled 1 BFTM is enabled When this bit is set to 1 the BFTM counter will start to count The counter will stop counting and the counter value will remain unchanged when the CEN bit is cleared to 0 by the application pro...

Page 296: ...23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved MIF Type Reset W0C 0 Bits Field Descriptions 0 MIF BFTM Compare Match Interrupt Flag 0 No compare match event occurs 1 Compare match event occurs When the counter value CNT is equal to the compare register value CMP a compare match event will occur and the corresponding interrupt flag MIF...

Page 297: ...W 0 Bits Field Descriptions 31 0 CNT BFTM Counter Value A 32 bit BFTM counter value is stored in this field which can be read or written on the fly BFTM Compare Value Register BFTMCMPR The register specifies the BFTM compare value Offset 0x00C Reset value 0xFFFF_FFFF 31 30 29 28 27 26 25 24 CMP Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 23 22 21 20 19 18 17 16 CMP Type Reset RW 1 RW 1 RW 1...

Page 298: ...Capture Compare Register CH0CCR Reload Register CRR DTG Dead Time Register DTG DTG Output Control Output Conf Registers Output Control Output Control Output Control MT_CH0O MT_CH0NO MT_CH1O MT_CH1NO MT_CH2O MT_CH2NO MT_CH3O MT_BRK Input Polarity Filter Clock Failure Event TI1 TI2 TI3 MT_BRK PSC PRESCALER Repetition Down Counter REPR Register Input Filter Polarity Selection Edge Detection Edge Dete...

Page 299: ...following events Update event 1 Update event 2 Trigger event Input capture event Output compare match Break event only interrupt MCTM Master Slave mode controller Supports 3 phase motor control and hall sensor interface Break input signals to assert the timer output signals in reset state or in a known state Functional Descriptions Counter Mode Up Counting In this mode the counter counts continuou...

Page 300: ...n direction Once the counter reaches 0 the Timer module generates an underflow event and the counter restarts to count once again from the counter reload value This action will continue repeatedly The counting direction bit DIR in the CNTCFR register should be set to 1 for the down counting mode When an update event 1 is generated by setting the UEV1G bit in the EVGR register to 1 the counter valu...

Page 301: ...d counting mode The count direction is updated by hardware automatically Setting the UEV1G bit in the EVGR register will initialise the counter value to 0 irrespective of whether the counter is counting up or down in the center aligned counting mode The UEV1IF bit in the INTSR register can be set to 1 according to the CMSEL field setting in the CNTCFR register When CMSEL 0x1 an underflow event wil...

Page 302: ...r At each counter overflow in the up counting mode At each counter underflow in the down counting mode At each counter overflow and underflow in the center aligned counting mode 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 0 1 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 3 2 Up Counting Down Counting Center Aligned Counting CK_CNT CNTR REPR UEV1 CNTR REPR UEV1 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 2 CK_CNT CNTR UEV1 ...

Page 303: ...L field to 0x7 in the MDCFR register Here the counter will act as an event counter The input event known as STI here can be selected by setting the TRSEL field to an available value except the value of 0x0 When the STI signal is selected as the clock source the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescaler It is impo...

Page 304: ...some MCTM functions which are triggered by a trigger signal rising edge Trigger Controller Block Edge Trigger Mux Level Trigger Mux Edge Detection ITI0 ITI1 ITI2 ITI0ED ITI1ED ITI2ED STIED TRCED TI0S0ED TI1S1ED TRSEL 2 0 TRSEL 3 0 1 0 Edge Trigger Mux TI0BED ITI0ED ITI1ED ITI2ED STI TRSEL 2 0 TRSEL 3 0 1 0 SW Set UEV1G Bit TI0S0 TI1S1 ITI0 ITI1 ITI2 Level Trigger Source Internal ITIx Channel input...

Page 305: ...start Pause Trigger Mode Figure 100 Slave Controller Diagram Restart Mode The counter and its prescaler can be reinitialised in response to an STI signal rising edge If the UEV1DIS bit is set to 1 to disable the update event then no update event will be generated however the counter and prescaler are still reinitialized when an STI rising edge occurs If the UEV1DIS bit in the CNTCFR register is cl...

Page 306: ...l polarity 0 STI source signal Sync polarity 1 Sync Figure 102 MCTM in Pause Mode Trigger Mode After the counter is disabled to count the counter can resume counting when an STI rising edge signal occurs When an STI rising edge occurs the counter will start to count from the current value in the counter Note that if the STI signal is selected to be sourced from the UEV1G bit software trigger the c...

Page 307: ...ve another MCTM or GPTM if exists which should be configured in the Slave Mode MCTMn Master MTO ITI GPTMm Slave MMSEL SMSEL TSE TRSEL Figure 104 Master MCTMn and Slave GPTMm Connection The Master Mode Selection bits MMSEL in the MDCFR register are used to select the MTO source for synchronising another slave MCTM or GPTM if exists Channel 0 Capture Compare event MTO UEV1G bit Counter enable signal...

Page 308: ...counter value is then compared with the register value CHxCCR Preload Register CHxCCR Shadow Register APB Bus Interface Capture Controller Capture Capture Transfer Compare Controller Compare Transfer Read CHxCCR CHxCCS CHxCCS CHxCCG CHxPRE CHxE CHxPSC Write CHxCCR Update Event 1 CHxCCR TM_CNT Figure 106 Capture Compare Block Diagram Capture Counter Value Transferred to CHxCCR When the channel is u...

Page 309: ... by setting the SMSEL field in the MDCFR register to 0x4 Enable the input capture mode by setting the CH0E and CH1E bits in the CHCTR register to 1 As the following diagram shows the high pulse width on the MT_CH0 pin will be captured into the CH1CCR register while the input period will be captured into the CH0CCR register after an input capture operation 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 4 MT_CH0 T...

Page 310: ... Channel 1 Input Stages Filter TI2FP TI2FN TI2F MT_CH2 CH2P Filter TI3FP TI3FN TI3F CH3P MT_CH3 TI2S2 TI3S2 TI2S3 TI3S3 TRCED CH2PRESCALER CH3PRESCALER TI2S2ED CH2PSC CH3PSC CH2CCS CH3CCS CH2PSC CH3PSC CH2CAP Event CH3CAP Event Edge Detection Edge Detection Edge Detection Edge Detection TI3S2ED TI2S3ED TI3S3ED fCLKIN fsampling fsampling TI2 TI3 Figure 110 Channel 2 and Channel 3 Input Stages Digit...

Page 311: ...gnal These channel outputs generate a wide variety of wide waveforms according to the configuration values of corresponding control bits as shown by the dashed box in the diagram Output Mode Controller CNTR CHxCCR CHxOM CHxOREF DTG CHDTG 0 CHxO_DT CHxNO_DT CHxNE CHxE CHxP CHxNP Output Enable Controller Output Enable Controller CHxE CHxNE CHMOE CHMOE CHOSSI CHOSSR CHOSSI CHOSSR CHxOIS CHxOISN CHxO ...

Page 312: ...direction and the relationship between the counter value and the CHxCCR content There are also two modes which will force the output into an inactive or active state irrespective of the CHxCCR content or counter values With regard to a more detailed description refer to the relative bit definition The Table 34 shows a summary of the output type setup Table 34 Compare Match Output Setup CHxOM Value...

Page 313: ... enable CHxCCR New value 3 Update CHxCCR value 1 2 3 TME CHxOREF UEV1 Update Event 1 Figure 114 Toggle Mode Channel Output Reference Signal CHxPRE 1 Counter Value CRR CHxCCR CHxOREF CHxOM 0x6 CHxCCIF CHxOREF Counter Value 100 0 CHxOM 0x7 CHxCCR CRR CHxOREF CHxCCIF CHxCCIF CHxOREF CRR Counter Value CHxOREF 0 CHxOREF 100 CHxCCR 0x0000 Figure 115 PWM Mode Channel Output Reference Signal and Counter i...

Page 314: ...CHxCCR Counter Value CHxOREF CHxCCIF CHxCCIF CHxOREF 0 Figure 116 PWM Mode Channel Output Reference Signal and Counter in Down counting Mode Up counting Down counting CRR 5 CHxCCR 3 CMSEL 0x1 CHxCCIF CHxCCR 4 CHxCCIF CHxCCR 5 CHxCCR 0 CHxCCIF CHxCCIF 100 0 0 1 2 3 4 5 4 3 2 1 0 1 Figure 117 PWM Mode 1 Channel Output Reference Signal and Counter in Centre aligned Counting Mode ...

Page 315: ...relative to the reference signal rising edge The CHxNO is the opposite of the CHxOREF signal except for the rising edge which is delayed with a dead time relative to the reference signal falling edge CHxP 0 CHxNP 0 CHMOE 1 CHxE 1 CHxNE 1 CHxOREF Dead time CHxO CHxNO When dead time greater than negative pulse CHxO CHxNO Dead time Dead time CHxP 0 CHxNP 0 CHMOE 1 CHxE 1 CHxNE 1 CHxOREF Dead time CHx...

Page 316: ...te Moreover a break event can also be generated by the software asserting the BRKG bit in the EVGR register even if the break function is disabled The MT_BRK input signal can be enabled by setting the BKE bit in the CHBRKCTR register The internal polarity of break activity function is logic high So the break input polarity can be selected by setting the BKP bit in CHBRKCTR register The BKE and BKP...

Page 317: ...hannel output behavior is as described below If complementary outputs are used the channel outputs a level signal first which can be selected to be either a disable or inactive level selected by configuring the CHOSSI bit in the CHBRKCTR register After the dead time duration the outputs will be changed to the idle state The idle state is determined by the CHxOIS CHxOISN bits in the CHBRKCFR regist...

Page 318: ...states when a break event occurs where the complementary outputs are enabled by setting both the CHxE and CHxNE bits to 1 CHMOE CHxOREF CHxO CHxNO Break event CHxO CHxNO CHxP 0 CHxOIS 0 CHxNP 0 CHxOISN 1 Dead time Dead time Dead time CHxP 0 CHxOIS 1 Dead time Dead time CHxNP 1 CHxOIS 1 Dead time Figure 122 Channel 0 2 Complementary Outputs with a Break Event Occurrence ...

Page 319: ...of the output being enabled by setting the CHxE bit to 1 and the complementary output being disabled by clearing the CHxNE to 0 when a break event occurs CHMOE CHxOREF CHxO CHxNO Break event CHxO CHxNO CHxP 0 CHxOIS 0 CHxNP 0 CHxOISN 1 Dead time CHxP 0 CHxOIS 1 CHxNP 0 CHxOIS 0 Dead time Dead time 0 Figure 123 Channel 0 2 Only One Output Enabled when Break Event Occurs ...

Page 320: ... in the active state Example Both CHxOIS and CHxOISN are set to active levels after a break event only the CHxO waveform is generated CHMOE CHxOREF CHxO CHxNO Break event CHxO CHxNO CHxP 0 CHxOIS 0 CHxNP 0 CHxOISN 0 CHxP 0 CHxOIS 1 CHxNP 0 CHxOIS 1 0 0 Figure 124 Hardware Protection When Both CHxO and CHxNO are in Active Condition CHMOE can be set automatically by update event 1 if the automatic o...

Page 321: ...utput enabled MT_CHx CHx_OREF xor CHxP dead time MT_CHx_OEN 0 Output enabled MT_CHxN not CHx_OREF xor CHxNP dead time MT_CHxN_OEN 0 1 0 0 Output disabled floating not driven by the timer MT_CHx floating MT_CHx_OEN 1 Output disabled floating not driven by the timer MT_CHxN floating MT_CHxN_OEN 1 1 0 1 Off State MT_CHx CHxP MT_CHx_OEN 0 Output enabled MT_CHxN CHx_OREF xor CHxNP MT_CHxN_OEN 0 1 1 0 O...

Page 322: ...when a rising edge on the STI occurs or the corresponding software update control bit is set Update Event 1 The UEV1DIS bit in the CNTCFR register can determine whether an update event 1 occurs or not When the update event 1 occurs the corresponding update event interrupt will be generated depending upon whether the update event 1 interrupt generation function is enabled or not by configuring the ...

Page 323: ... occurs COMPRE 1 CHOSSR 1 CHxP CHxNP 0 CHDTG 0 Update Event 2 CHxE CHxNE Shadow CHxE Shadow CHxNE CHxOM Shadow CHxOM CHxO CHxNO PWM1 PWM1 Forced Inactive Forced Inactive Forced Active Forced Active Figure 126 CHxE CHxNE and CHxOM Updated by Update Event 2 An update event 2 can be generated by setting the software update bit UEV2G in the EVGR register or by the rising edge of the STI signal if the ...

Page 324: ... the TME bit at a high state until the update event 1 occurs or the TME bit is cleared to 0 by software If the TME bit is cleared to 0 using software the counter will be stopped and its value held If the TME bit is automatically cleared to 0 by a hardware update event 1 the counter will be reinitialised Trigger by S W Trigger by STI Cleared by Update Event Flag is set by compare match and cleared ...

Page 325: ...egister After an STI rising edge trigger occurs in the single pulse mode the CHxOREF signal will immediately be forced to the state to which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigger source is ...

Page 326: ...s into the counting down stage the PWM uses the value in CHxACR as down count compare value The figure 130 is shown as an example for asymmetric PWM mode in Center aligned Counting mode Note Asymmetric PWM mode can only be operated in Center aligned Counting mode 2 3 4 5 6 7 0 1 8 5 4 3 2 1 0 7 6 2 3 4 5 6 7 1 8 5 4 3 2 1 0 7 6 2 3 4 5 6 7 1 8 5 4 3 2 1 7 6 CNTR CHxOREF CHxOREF CHxOREF CHxOREF PWM...

Page 327: ... modes Using One Timer to Trigger Another Timer to Start or Stop Counting Configure MCTM to be in the master mode and to send its channel 0 Output Reference signal CH0OREF as a trigger output MMSEL 0x4 Configure the MCTM CH0OREF waveform Configure the GPTM to receive its input trigger source from the MCTM trigger output TRSEL 0xA Configure GPTM to operate in the pause mode SMSEL 0x5 Enable GPTM by...

Page 328: ...nt UEV as the trigger output MMSEL 0x2 Configure the MCTM period by setting the CRR register Configure GPTM to get the input trigger source from the MCTM trigger output TRSEL 0xA Configure GPTM to be in the slave trigger mode SMSEL 0x6 Start MCTM by writing 1 to the TME bit 14 15 00 01 02 FB FC FA 03 13 fCLKIN MCTM CNTR GPTM CNTR Software clearing GPTM TME bit GPTM TEVIF FD MCTM UEV1IF Figure 132 ...

Page 329: ...e slave trigger mode SMSEL 0x6 Enable the MCTM master timer synchronisation function by setting the TSE bit in the MDCFR register to 1 to synchronise the slave timer Configure GPTM to receive its input trigger source from the MCTM trigger output TRSEL 0xA Configure GPTM to be in the slave trigger mode SMSEL 0x6 TI0 TI0FP fDTS fCLKIN TI0S0ED MCTM TME bit MCTM TEVIF TSE 1 Delay MCTM CK_PSC 0 1 2 3 4...

Page 330: ...ure TI0BED to be connected to STI TRSEL 0x8 Configure the counter to be in the slave restart mode SMSEL 0x4 Enable GPTM TME 1 MCTM Select GPTM MTO to be the STI source of MCTM TRSEL 0xA Enable the CHxE CHxNE and CHxOM preload function COMPRE 1 Select the rising edge on STI to generate an update event 2 COMUS 1 Enable the update event 2 interrupt UEV2IE 1 In the update event 2 ISR write CHxE CHxNE ...

Page 331: ...f the GCCR register is located in the CKCU unit and use to monitor the high speed external clock HSE source If the CKMEN bit is enabled and when hardware detects HSE clock stuck at low high state internal hardware will automatically switch the system clock to internal high speed RC clock HSI to protect the system safety 3 When the MCTMEN and CKMEN control bits of the CKCU lock protection mode is e...

Page 332: ...x0000_0000 CH2CCR 0x098 Channel 2 Capture Compare Register 0x0000_0000 CH3CCR 0x09C Channel 3 Capture Compare Register 0x0000_0000 CH0ACR 0x0A0 Channel 0 Asymmetric Compare Register 0x0000_0000 CH1ACR 0x0A4 Channel 1 Asymmetric Compare Register 0x0000_0000 CH2ACR 0x0A8 Channel 2 Asymmetric Compare Register 0x0000_0000 CH3ACR 0x0AC Channel 3 Asymmetric Compare Register 0x0000_0000 Register Descript...

Page 333: ... count up and count down period 9 8 CKDIV Clock Division These two bits define the frequency ratio between the timer clock fCLKIN and the dead time clock fDTS The dead time clock is also used as the digital filter sampling clock 00 fDTS fCLKIN 01 fDTS fCLKIN 2 10 fDTS fCLKIN 4 11 Reserved 1 UGDIS Update event 1 interrupt generation disable control 0 Any of the following events will generate an upd...

Page 334: ...0000 31 30 29 28 27 26 25 24 Reserved SPMSET Type Reset RW 0 23 22 21 20 19 18 17 16 Reserved MMSEL Type Reset RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved SMSEL Type Reset RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved TSE Type Reset RW 0 Bits Field Descriptions 24 SPMSET Single Pulse Mode Setting 0 Counter counts normally irrespective of whether a update event occurred or not 1 Counter stops counting ...

Page 335: ...gger output 010 Update Mode The update event 1 is used as the trigger output according to one of the following cases when the UEV1DIS bit is cleared to 0 Counter overflow underflow Software setting UEV1G Slave has trigger input when used in slave restart mode 011 Capture Compare Mode When a Channel 0 capture or compare match event occurs it will generate a positive pulse which is used as the maste...

Page 336: ...ted 101 Pause Mode The counter starts to count when the selected trigger input STI is high The counter stops counting on the instant not being reset when the STI signal changes its state to a low level Both the counter start and stop control are determined by the STI signal 110 Trigger Mode The counter starts to count from the original value in the counter on the rising edge of the selected trigge...

Page 337: ...Field Descriptions 3 0 TRSEL Trigger Source Selection These bits are used to select the trigger input STI for counter synchronization 0000 Software Trigger by setting the UEV1G bit 0001 Channel 0 filtered input TI0S0 0010 Channel 1 filtered input TI1S1 0011 Reserved 1000 Channel 0 Edge Detector TI0BED 1001 Internal Timer Trigger 0 ITI0 1010 Internal Timer Trigger 1 ITI1 1011 Internal Timer Trigger...

Page 338: ...capture compare preload function is enabled by setting the COMPRE bit to 1 8 COMPRE Capture Compare Preloaded Enable Control 0 CHxE CHxNE and CHxOM bits are not preloaded 1 CHxE CHxNE and CHxOM bits are preloaded If this bit is set to 1 the corresponding capture compare control bits including the CHxE CHxNE and CHxOM bits will be updated when the update event 2 occurs 1 CRBE Counter Reload registe...

Page 339: ...Channel 0 Capture Input Source Prescaler Setting These bits define the effective events of the channel 0 capture input Note that the prescaler is reset once the Channel 0 Capture Compare Enable bit CH0E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 0 capture input signal is chosen for each active event 01 Channel 0 Capture input signal is chosen for every 2 ev...

Page 340: ...110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Channel 1 Input Configuration Register CH1ICFR This register specifies the channel 1 input mode configuration Offset 0x024 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CH1PSC CH1CCS Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved TI1F Type R...

Page 341: ...is cleared to 0 3 0 TI1F Channel 1 Input Source TI1 Filter Setting These bits define the frequency divide ratio used to sample the TI1 signal The Digital filter in the MCTM is an N event counter where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fSAMPLING fCLKIN N 2 0010 fSAMPLING fCLKIN N 4 0011 fSAMPLING fC...

Page 342: ...re input Note that the prescaler is reset once the Channel 2 Capture Compare Enable bit CH2E in the Channel Control register named CHCTR is cleared to 0 00 No prescaler channel 2 capture input signal is chosen for each active event 01 Channel 2 Capture input signal is chosen for every 2 events 10 Channel 2 Capture input signal is chosen for every 4 events 11 Channel 2 Capture input signal is chose...

Page 343: ...110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Channel 3 Input Configuration Register CH3ICFR This register specifies the channel 3 input mode configuration Offset 0x02C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved CH3PSC CH3CCS Type Reset RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved TI3F Type R...

Page 344: ...is cleared to 0 3 0 TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divide ratio used to sample the TI3 signal The digital filter in the GPTM is an N event counter where N is defined as how many valid transitions are necessary to output a filtered signal 0000 No filter the sampling clock is fSYSTEM 0001 fSAMPLING fCLKIN N 2 0010 fSAMPLING fCLKIN N 4 0011 fSAMPLING fC...

Page 345: ...mmediate Active Mode is enabled The CH0OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH0IMAE bit is available only if channel 0 is configured operate in PWM mode 1 or PWM...

Page 346: ...0111 PWM mode 2 During up counting channel 0 is has an inactive level when CNTR CH0CCR or otherwise has an active level During down counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 0 has an active level when CNTR CH0CCR or otherwise has an inactive level During down counting channel 0 has an inactive le...

Page 347: ...diate Active Mode is enabled The CH1OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH1IMAE bit is available only if channel 1 is configured to be operated in PWM mode 1 or...

Page 348: ... 0111 PWM mode 2 During up counting channel 1 has an inactive level when CNTR CH1CCR or otherwise has an active level During down counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 1 has an active level when CNTR CH1CCR or otherwise has an inactive level During down counting channel 1 has an inactive leve...

Page 349: ...ate Active Mode is enabled The CH2OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH2IMAE bit is available only if the channel 2 is configured to be operated in PWM mode 1 ...

Page 350: ... 0111 PWM mode 2 During up counting channel 2 has an inactive level when CNTR CH2CCR or otherwise has an active level During down counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 2 has an active level when CNTR CH2CCR or otherwise has an inactive level During down counting channel 2 has an inactive leve...

Page 351: ...diate Active Mode is enabled The CH3OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CCR values The effective duration ends automatically at the next overflow or underflow event Note The CH3IMAE bit is available only if channel 3 is configured to be operated in PWM mode 1 or...

Page 352: ... 0111 PWM mode 2 During up counting channel 3 has an inactive level when CNTR CH3CCR or otherwise has an active level During down counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level 1110 Asymmetric PWM mode 1 During up counting channel 3 has an active level when CNTR CH3CCR or otherwise has an inactive level During down counting channel 3 has an inactive leve...

Page 353: ... CH3O is generated on the corresponding output pin depending on the condition of the CHMOE CHOSSI CHOSSR and CH3OIS bits 5 CH2NE Channel 2 Capture Compare Complementary Enable 0 Off Channel 2 complementary output CH2NO is not active The CH2NO level is then determined by the CHMOE CHOSSI CHOSSR CH2OIS CH2OISN and CH2E bits 1 On Channel 2 complementary output CH2NO is generated on the corresponding ...

Page 354: ...its 1 On Channel 1 output signal CH1O is generated on the corresponding output pin depending on the condition of the CHMOE CHOSSI CHOSSR CH1OIS CH1OISN and CH1NE bits 1 CH0NE Channel 0 Capture Compare Complementary Enable 0 Off Channel 0 complementary output CH0NO is not active The CH0NO level is then determined by the condition of the CHMOE CHOSSI CHOSSR CH0OIS CH0OISN and CH0E bits 1 On Channel ...

Page 355: ...3 Output is active low 5 CH2NP Channel 2 Capture Compare Complementary Polarity 0 Channel 2 Output is active high 1 Channel 2 Output is active low 4 CH2P Channel 2 Capture Compare Polarity When Channel 2 is configured as an input CH2CCS 0x1 0x2 0x3 0 capture event occurs on a Channel 2 rising edge 1 capture event occurs on a Channel 2 falling edge When Channel 2 is configured as an output CH2CCS 0...

Page 356: ...erved Type Reset 7 6 5 4 3 2 1 0 Reserved CH3OIS CH2OISN CH2OIS CH1OISN CH1OIS CH0OISN CH0OIS Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 6 CH3OIS MT_CH3O Output Idle State 0 Channel 3 output CH3O 0 when CHMOE 0 1 Channel 3 output CH3O 1 when CHMOE 0 5 CH2OISN MT_CH2NO Output Idle State 0 Channel 2 complementary output CH2NO 0 after a dead time when CHMOE 0 1 Channel 2 co...

Page 357: ... RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved CHAOE CHMOE Reserved BKP BKE Type Reset RW 0 RW 0 RW 1 RW 0 Bits Field Descriptions 31 24 CHDTG Channel Dead Time Duration Definition CHDTG 7 5 0xx Channel Dead Time CHDTG 7 0 tdtg with tdtg tDTS CHDTG 7 5 10x Channel Dead Time 64 CHDTG 5 0 tdtg with tdtg 2 tDTS CHDTG 7 5 110 Channel Dead Time 32 CHDTG 4 0 tdtg with tdtg 8 tDTS CHDTG 7 5 111 Channel Dead Ti...

Page 358: ... fSAMPLING fCLKIN N 4 0011 fSAMPLING fCLKIN N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 5 CHAOE Channel Automatic Output E...

Page 359: ...enabled 10 TEVIE Trigger event Interrupt Enable 0 Trigger event interrupt is disabled 1 Trigger event interrupt is enabled 9 UEV2IE Update event 2 Interrupt Enable 0 Update event 2 interrupt is disabled 1 Update event 2 interrupt is enabled 8 UEV1IE Update event 1 Interrupt Enable 0 Update event 1 interrupt is disabled 1 Update event 1 interrupt is enabled 3 CH3CCIE Channel 3 Capture Compare Inter...

Page 360: ...lag is set and then the CHMOE bit will be cleared 10 TEVG Trigger Event Generation The trigger event TEV can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 The TEVIF flag is set 9 UEV2G Update Event 2 Generation The update event 2 UEV2 can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 Update the CHxE CHxNE and CHxOM b...

Page 361: ...ured as an input the counter value is captured into the CH2CCR register and then the CH2CCIF bit is set If Channel 2 is configured as an output the CH2CCIF bit is set 1 CH1CCG Channel 1 Capture Compare Generation A Channel 1 capture compare event can be generated by setting this bit It is cleared by hardware automatically 0 No action 1 Capture compare event is generated on channel 1 If Channel 1 i...

Page 362: ...er Event Interrupt Flag This flag is set by hardware when a trigger event occurs and is cleared by software 0 No trigger event occurs 1 Trigger event occurs 9 UEV2IF Update Event 2 Interrupt Flag This bit is set by hardware when an update event 2 occurs and is cleared by software 0 No update event 2 occurs 1 Update event 2 occurs 8 UEV1IF Update Event 1 Interrupt Flag This bit is set by hardware w...

Page 363: ...ed counting mode It is cleared by software Channel 3 is configured as an input 0 No input capture occurs 1 Input capture occurs This bit is set by hardware when a capture event occurs It is cleared by software or by reading the CH3CCR register 2 CH2CCIF Channel 2 Capture Compare Interrupt Flag Channel 2 is configured as an output 0 No match event occurs 1 The contents of the counter CNTR have matc...

Page 364: ...aligned counting mode It is cleared by software Channel 0 is configured as an input 0 No input capture occurs 1 Input capture occurs This bit is set by hardware on a capture event It is cleared by software or by reading the CH0CCR register Timer Counter Register CNTR This register stores the timer counter value Offset 0x080 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 ...

Page 365: ...29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 PSCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 PSCV Prescaler Value These bits are used to specify the prescaler value to generate the counter clock frequency fCK_CNT fCK_CNT fCK_PSC PSC...

Page 366: ... 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 15 0 CRV Counter Reload Value The CRV is the reload value which is loaded into the actual counter register Timer Repetition Register REPR This register specifies the timer repetition counter value Offset 0x08C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 1...

Page 367: ...d Type Reset 15 14 13 12 11 10 9 8 CH0CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH0CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH0CCV Channel 0 Capture Compare Value When Channel 0 is configured as an output The CH0CCR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal ...

Page 368: ...d Type Reset 15 14 13 12 11 10 9 8 CH1CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH1CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH1CCV Channel 1 Capture Compare Value When Channel 1 is configured as an output The CH1CCR value is compared with the counter value and the comparison result is used to trigger the CH1OREF output signal ...

Page 369: ...d Type Reset 15 14 13 12 11 10 9 8 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH2CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH2CCV Channel 2 Capture Compare Value When Channel 2 is configured as an output The CH2CCR value is compared with the counter value and the comparison result is used to trigger the CH2OREF output signal ...

Page 370: ...d Type Reset 15 14 13 12 11 10 9 8 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 CH3CCV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 CH3CCV Channel 3 Capture Compare Value When Channel 3 is configured as an output The CH3CCR value is compared with the counter value and the comparison result is used to trigger the CH3OREF output signal ...

Page 371: ...ue When channel 0 is configured as asymmetric PWM mode and the counter is counting down the value written is this register will be compared to the counter Channel 1 Asymmetric Compare Register CH1ACR This register specifies the timer channel 1 asymmetric compare value Offset 0x0A4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 ...

Page 372: ...ue When channel 2 is configured as asymmetric PWM mode and the counter is counting down the value written is this register will be compared to the counter Channel 3 Asymmetric Compare Register CH3ACR This register specifies the timer channel 3 asymmetric compare value Offset 0x0AC Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 ...

Page 373: ...ompare Register match CSECFLAG OVFLAG CMFLAG CSECIEN OVIEN CMIEN CSECWEN OVWEN CMWEN RTCSRC CK_RTC CK_SECOND RTCINT RTCWAKEUP CK_LSE CK_LSI APB Bus 24 24 set set set CMPCLR LSE OSC LSI RC OSC To NVIC To EXTI and PWRCU 1 5 V Core Power Domain VDD15 VDD Power Domain APB Interface Figure 135 RTC Block Diagram Features 24 bit up counter for counting elapsed time Programmable clock prescaler Division f...

Page 374: ...de LSESM Setting in the RTCCR Register Operating Current Startup Time Normal startup 0 2 0 μA Above 500 ms Fast startup 1 3 5 μA Below 300 ms VDD 3 3 V and LSE clock 32 768 Hz these values are only for reference actual values are dependent on the specification of the external 32 768 kHz crystal RTC Counter Operation The RTC provides a 24 bit up counter which increments at the falling edge of the C...

Page 375: ... register definitions for more details RTCOUT Output Pin Configuration The following table shows RTCOUT output format according to the mode polarity and event selection setting Table 40 RTCOUT Output Mode and Active Level Setting ROWM ROES RTCOUT Output Waveform 0 Pulse mode 0 Compare match RTCCMP 4 RTCCNT 3 4 5 TR RTCOUT ROAP 0 RTCOUT ROAP 1 ROLF 1 Second clock RTCCMP X RTCCNT 3 4 5 TR TR TR RTCO...

Page 376: ...hich is incremented by the CK_SECOND clock Offset 0x000 Reset value 0x0000_0000 Reset by VDD15 Power Domain reset only 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 RTCCNTV Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RTCCNTV Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RTCCNTV Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO ...

Page 377: ... 1 0 RTCCMPV Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 23 0 RTCCMPV RTC Compare Match Value A match condition happens when the value in the RTCCNT register is equal to RTCCMP value An interrupt can be generated if the CMIEN bit in the RTCIWEN register is set When the CMPCLR bit in the RTCCR register is set to 0 and a match condition happens the CMFLAG bit in the RT...

Page 378: ...nactive level after software has read this bit 19 ROAP RTCOUT Output Active Polarity 0 Active level is high 1 Active level is low 18 ROWM RTCOUT Output Waveform Mode 0 Pulse mode The output pulse duration is one RTC clock CK_RTC period 1 Level mode The RTCOUT signal will remain at an active level until the ROLF bit is cleared by software reading the ROLF bit 17 ROES RTCOUT Output Event Selection 0...

Page 379: ...es less operating power 1 Fast startup but requires higher operating current 4 CMPCLR Compare Match Counter Clear 0 24 bit RTC counter is not affected when compare match condition occurs 1 24 bit RTC counter is cleared when compare match condition occurs 3 LSEEN LSE oscillator Enable Control 0 LSE oscillator is disabled 1 LSE oscillator is enabled 1 RTCSRC RTC Clock Source Selection 0 LSI oscillat...

Page 380: ... is suggested to read in the RTC IRQ handler and should be taken care when software polling is used 1 CMFLAG Compare Match Condition Flag 0 Compare match condition does not occur since the last RTCSR register read operation 1 Compare match condition has occurred since the last RTCSR register read operation This bit is set by hardware on the CK_SECOND clock falling edge when the RTCCNT register val...

Page 381: ...ions 10 OVWEN Counter Overflow Wakeup Enable 0 Counter overflow wakeup is disabled 1 Counter overflow wakeup is enabled 9 CMWEN Compare Match Wakeup Enable 0 Compare match wakeup is disabled 1 Compare match wakeup is enabled 8 CSECWEN Counter Clock CK_SECOND Wakeup Enable 0 Counter Clock CK_SECOND wakeup is disabled 1 Counter Clock CK_SECOND wakeup is enabled 2 OVIEN Counter Overflow Interrupt Ena...

Page 382: ...an be stopped when the processor is in the debug or sleep mode The register write protection function can be enabled to prevent an unexpected change in the Watchdog timer configuration KEY WDTV Reload 12 bit Down Counter WDTD Prescaler 1 2 4 8 128 0 WDTD WDTUF WDTERR RSKEY 15 0 WDTRS WPSC 2 0 Underflow WDT Error WDT_RSTn Clear WDTRSTEN Read WDTSR Register LSI RC 32 kHz LSE OSC 32 768 kHz 0 1 CK_WD...

Page 383: ...ed To prevent this situation from occurring the reload operation must be executed in such a way that the value of the Watchdog timer counter is limited within a delta value WDTD If the Watchdog timer counter value is greater than the delta value and a reload operation is executed a Watchdog Timer error will occur The Watchdog timer error will generate a Watchdog reset if the related functional con...

Page 384: ...ng to the WDTCR register with WDTRS 1 and RSKEY 0x5FA0 Write to the WDTPR register to lock all the Watchdog timer registers except for WDTCR and WDTPR The Watchdog timer counter should be reloaded again within the delta value WDTD 0 WDTD WDTV 0xFFF Time Reload counter when counter WDTD Normal behavior Watchdog Timer underflow Reload counter when counter WDTD Start counter Reset occurred If WDTRSTE...

Page 385: ...rol Register WDTCR This register is used to reload the Watchdog timer Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 RSKEY Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 RSKEY Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved WDTRS Type Reset WO 0 Bits Field Descriptions 31 16 RSKEY Watchd...

Page 386: ...d with the WDTV value and count down 15 14 WDTSHLT Watchdog Timer Sleep Halt 00 The Watchdog runs when the system is in the Sleep mode or Deep Sleep1 mode 01 The Watchdog runs when the system is in the Sleep mode and halts in Deep Sleep1 mode 10 or 11 The Watchdog halts when the system is in the Sleep mode and Deep Sleep1 mode Note that the Watchdog timer always halts when the system is in Deep Sl...

Page 387: ... Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bits Field Descriptions 14 12 WPSC Watchdog Timer Prescaler Selection 000 1 1 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 11 0 WDTD Watchdog Timer Delta Value Define the permitted range to reload the Watchdog timer If the Watchdog timer counter value is less than or equal to WDTD writing to the WDTCR register with WDTRS 1 and RSKEY 0x...

Page 388: ...C 0 WC 0 Bits Field Descriptions 1 WDTERR Watchdog Timer Error 0 No Watchdog timer error has occurred since the last read of this register 1 A Watchdog timer error has occurred since the last read of this register Note A reload operation when the Watchdog timer counter value is larger than WDTD causes a Watchdog timer error Note that this bit is a write one clear flag 0 WDTUF Watchdog timer Underf...

Page 389: ...ts Field Descriptions 15 0 PROTECT Watchdog Timer Register Protection For write operation 0x35CA Disable the Watchdog timer register write protection Others Enable the Watchdog timer register write protection For read operation 0x0000 Watchdog timer register write protection is disabled 0x0001 Watchdog timer register write protection is enabled This register is used to enable disable the Watchdog ...

Page 390: ... Field Descriptions 4 WDTLOCK Watchdog Timer Lock Mode 0 This bit is only set to 0 on any reset It cannot be cleared by software 1 This bit is set once only by software and locks the Watchdog timer function Software can set this bit to 1 at any time Once the WDTLOCK bit is set the function and registers of the Watchdog timer cannot be modified or disabled including the Watchdog timer clock source ...

Page 391: ...ration registers are used to setup different kinds of duty cycle implementation for the SCL pulse The SDA line which is connected to the whole I2 C bus is a bidirectional data line between the master and slave devices used for the transmission and reception of data The I2 C module also has an arbitration detection function to prevent the situation where more than one master attempts to transmit da...

Page 392: ...d serial clock SCL lines to carry information between the interconnected devices connected to the bus The SCL and SDA lines are both bidirectional and must be connected to a pull high resistor When the I2 C bus is in the free or idle state both pins are at a high level to perform the required wired AND function for multiple connected devices START and STOP Conditions A master device can initialize...

Page 393: ...ondition P STOP Condition SDA SCL Figure 139 START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock The SDA data state can only be changed when the clock signal on the SCL line is in a low state SDA SCL Stable data line Change of data allowed Figure 140 Data Validity ...

Page 394: ...t length slave address which the master device wants to communicate with a R W bit and an ACK bit The R W bit defines the direction of the data transfer R W 0 Write The master transmits data to the addressed slave R W 1 Read The master receives data from the addressed slave The slave address can be assigned through the ADDR field in the I2CADDR register The slave device sends back the acknowledge ...

Page 395: ... and an address byte that usually determines which slave will be selected by the master The header byte is composed of a leading 11110 the 10th and 9th bits of the slave address The second byte is the remaining 8 bits of the slave device address S 1 W S START condition W Write command Ack Acknowledge A9 A0 10 bit Address 1 1 1 0 Data A9 A8 Ack A7 A6 Ack A4 A3 A2 A0 A1 A5 MSB LSB Figure 142 10 bit ...

Page 396: ...lock If the slave device returns a Not Acknowledge NACK signal to the master device the master device can generate a STOP signal to terminate the data transfer or generate a repeated START signal to restart the transfer If the master device sends a Not Acknowledge NACK signal to the slave device the slave device should release the SDA line for the master device to generate a STOP signal to termina...

Page 397: ... START signal at approximately the same time an arbitration procedure will occur Arbitration takes place on the SDA line and can continue for many bits The arbitration procedure gives a higher priority to the device that transmits serial data with a binary low bit logic low Other master devices which want to transmit binary high bits logic high will lose the arbitration As soon as a master loses t...

Page 398: ... an idle state Address Mask Enable The I2 C module provides an address mask function for users to decide which address bit can be ignored during the comparison with the address frame sent from the master The ADRS flag will be asserted when the unmasked address bits and the address frame sent from the master are matched Note that this function is only available in the slave mode For instance the us...

Page 399: ...ster Data Frame The data to be transmitted to the slave device must be transferred to the I2CDR register The TXDE bit in the I2CSR register is set to indicate that the I2CDR register is empty which results in the SCL line being held at a logic low state New data must then be transferred to the I2CDR register to continue the data transfer process Writing a data into the I2CDR register will clear th...

Page 400: ...will be set twice in the 10 bit addressing mode The first time the ADRS bit is set is when the 10 bit address is sent and the acknowledge signal from the slave device is received The second time the ADRS bit is set is when the header byte is sent and the slave acknowledge signal is received In order to receive the following data frame the ADRS bit must be cleared to 0 if it has been set to 1 The A...

Page 401: ...the slave device The STOP bit can be set to terminate the data transfer process or re assign the I2CTAR register to restart a new transfer S STA Address A ADRS Data1 A Data2 A DataN P 7 bit Master Receiver S STA Header A Data1 A Data2 A DataN P 10 bit Master Receiver Address A BEH1 BEH1 BEH4 BEH1 BEH1 BEH4 BEH2 BEH2 BEH2 BEH2 BEH1 cleared by reading I2CSR register BEH2 cleared by reading I2CDR reg...

Page 402: ...n be written into the I2CDR register to continue the data transfer process Writing a data into the I2CDR register will clear the TXDE bit Receive Not Acknowledge When the slave device receives a Not Acknowledge signal the RXNACK bit in the I2CSR Register is set but it will not hold the SCL line Writing 1 to RXNACK will clear the RXNACK flag STOP Condition When the slave device detects a STOP condi...

Page 403: ...XDNE bit has been set to 1 the RXBF bit in the I2CSR register will be set to 1 and the SCL line will be held at a logic low state When this situation occurs data from the I2CDR register should be read to continue the data transfer process The RXDNE flag bit can be cleared after reading the I2CDR register STOP Condition When the slave device detects a STOP condition the STO flag bit in the I2CSR re...

Page 404: ...et STOP Slave case Writing data to I2CDR register GCS I2 C is addressed as slave through general call Reading I2CSR register ADRS Master I2 C is sent over address frame and is returned an ACK from slave Note Reference Fig 147 and Fig 148 Slave I2 C is addressed as slave device Note Reference Fig 149 and Fig 150 Reading I2CSR register STA Master sends a START signal Reading I2CSR register RXBF Rece...

Page 405: ...S flags is asserted The timeout counter will stop counting when the ENTOUT bit is cleared However the counter will also stop counting when one of the conditions listed as follows occurs The I2 C slave module is not addressed The I2 C slave module detects a STOP signal The I2 C master module sends a STOP signal The ARBLOS or BUSERR flag in the I2CSR register are asserted If the timeout counter unde...

Page 406: ... in I2CSLPGR register 13 COMBFILTEREN SDA or SCL Input Combinational Filter Enable Bit 0 Combinational filter is disabled 1 Combinational filter is enabled 12 ENTOUT I2 C Timeout Function Enable Control 0 Timeout Function is disabled 1 Timeout Function is enabled This bit is used to enable or disable the I2 C timeout function When the I2CEN bit is cleared to 0 the ENTOUT bit will be automatically ...

Page 407: ...te is received 1 Send an Acknowledge ACK signal after a byte is received When the I2CEN bit is cleared to 0 the AA bit is automatically cleared to 0 by hardware I2 C Interrupt Enable Register I2CIER This register specifies the corresponding I2 C interrupt enable bits Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved RXBFIE TXDEIE RXDN...

Page 408: ...to 0 by hardware 8 ARBLOSIE Arbitration Loss Interrupt Enable Bit in the I2 C multi master mode 0 Interrupt is disabled 1 Interrupt is enabled When the I2CEN bit in the I2CCR register is cleared to 0 this bit is cleared to 0 by hardware 3 GCSIE General Call Slave Interrupt Enable Bit 0 Interrupt is disabled 1 Interrupt is enabled When the I2CEN bit in the I2CCR register is cleared to 0 this bit is...

Page 409: ... 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ADDR Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 ADDR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 ADDR Device Address The register indicates the I2 C device address When the I2 C device is used in the 7 bit addressing mode only the ADDR 6 0 bits will be compared with the r...

Page 410: ...tched as a master device on the I2 C bus when the I2CTAR register is assigned and the I2 C bus is idle The MASTER bit is cleared by hardware when software disables the I2 C bus by clearing the I2CEN bit to 0 or sends a STOP condition to the I2 C bus or the bus error is detected This bit is set and cleared by hardware and is a read only bit 19 BUSBUSY Bus Busy 0 I2 C bus is idle 1 I2 C bus is busy ...

Page 411: ...START or STOP condition in a transfer process Writing a 1 to this bit will clear the BUSERR flag In Master Mode Once the Bus Error event occurs both the SDA and SCL lines are released by hardware and the BUSERR flag is asserted The application software has to clear the BUSERR flag before the next address byte is transmitted In Slave Mode Once a misplaced START or STOP condition has been detected b...

Page 412: ...n Slave Mode 0 I2 C interface is not addressed 1 I2 C interface is addressed as slave When the I2 C interface has received the calling address that matches the address defined in the I2CADDR register together with the AA bit being set to 1 in the I2CCR register it will be switched to a slave mode This flag is cleared automatically after the I2CSR register has been read 1 STO STOP Condition Detecte...

Page 413: ... 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 SHPG Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 SHPG Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 SHPG SCL Clock High Period Generation High period duration setting SCLHIGH TPCLK SHPG d where TPCLK is the APB bus peripheral clock PCLK period and d value depends on the setting of the...

Page 414: ...RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 SLPG SCL Clock Low Period Generation Low period duration setting SCLLOW TPCLK SLPG d where TPCLK is the APB bus peripheral clock PCLK period and d value depends on the setting of the SEQFILTER field in the I2 C Control Register I2CCR If SEQFILTER 00 d 6 If SEQFILTER 01 d 8 If SEQFILTER 10 or 11 d 9 SCL High period duration TPCLK SHPG d Low period duratio...

Page 415: ...6 5 4 3 2 1 0 DATA Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 0 DATA I2 C Data Register For the transmitter mode a data byte which is transmitted to a slave device can be assigned to these bits The TXDE flag is cleared if the application software assigns new data to the I2CDR register For the receiver mode a data byte is received bit by bit from MSB to LSB through...

Page 416: ...t slave address 1 Read direction from target slave address If this bit is set to 1 in the 10 bit master receiver mode the I2 C interface will initiate a byte with a value of 11110XX0b in the first header frame and then continue to deliver a byte with a value of 11110XX1b in the second header frame by hardware automatically 9 0 TAR Target Slave Address The I2 C interface will assign a START signal ...

Page 417: ...served Type Reset 15 14 13 12 11 10 9 8 Reserved ADDMR Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 ADDMR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 0 ADDMR Address Mask Control Bit The ADDMR i is used to specify whether the ith bit of the ADDR in the I2CADDR register is masked and is compared with the received address frame or not on the I2 C bus The register is only use...

Page 418: ...bus Offset 0x024 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved ADDSR Type Reset RO 0 RO 0 7 6 5 4 3 2 1 0 ADDSR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 9 0 ADDSR Address Snoop Once the I2CEN bit is enabled the calling address value on the I2 C bus will automatically b...

Page 419: ...out counter clock frequency fI2CTO The timeout clock frequency is obtained using the formula fI2CTO fPCLK 2PSC PSC 0 fI2CTO fPCLK 20 fPCLK PSC 1 fI2CTO fPCLK 21 fPCLK 2 PSC 2 fI2CTO fPCLK 22 fPCLK 4 PSC 7 fI2CTO fPCLK 27 fPCLK 128 15 0 TOUT I2 C Timeout Counter Preload Value The TOUT field is used to define the counter preloaded value The counter value is reloaded when any of the following conditi...

Page 420: ... using the SEL and SCK signals to indicate the start of the data communication and the data sampling rate To receive the data bits the streamlined data bits which range from 1 bit to 16 bits specified by the DFL field in the SPICR1 register are latched on a specific clock edge and stored in the data register or in the RX FIFO Data transmission is carried in a similar way but with the reverse seque...

Page 421: ...MODE bit is set the SPI module is configured as a master and will generate the serial clock on the SCK pin The data stream will transmit data in the shift register to the MOSI pin on the serial clock edge The SEL pin is active during the full data transmission When the SELAP bit in the SPICR1 register is set the SEL pin is active high during the complete data transactions When the SELM bit in the ...

Page 422: ...formats contained in the SPI interface Table 46 shows how to configure these formats by setting the FORMAT field in the SPICR1 register Table 46 SPI Interface Format Setup FORMAT 2 0 CPOL CPHA 001 0 0 010 0 1 110 1 0 101 1 1 Others Reserved CPOL 0 CPHA 0 In this format the received data is sampled on the SCK line rising edge while the transmitted data is changed on the SCK line falling edge In the...

Page 423: ...L 0 CPHA 0 CPOL 0 CPHA 1 In this format the received data is sampled on the SCK line falling edge while the transmitted data is changed on the SCK line rising edge In the master mode the first bit is driven when data is written into the SPIDR register In the slave mode the first bit is driven at the first SCK clock rising edge Figure 155 shows the single data byte transfer timing SCK MISO MOSI TX ...

Page 424: ...CPHA 0 In this format the received data is sampled on the SCK line falling edge while the transmitted data is changed on the SCK line rising edge In the master mode the first bit is driven when data is written into the SPIDR register In the slave mode the first bit is driven when the SEL signal changes to an active level Figure 157 shows the single byte transfer timing of this format SCK MISO MOSI...

Page 425: ...he SCK line falling edge In the master mode the first bit is driven when data is written into the SPIDR register In the slave mode the first bit is driven at the first SCK falling edge Figure 159 shows the single byte transfer timing of this format SCK MISO MOSI TX 7 TX 6 TX 5 TX 4 TX 3 TX 2 TX 1 TX 0 RX 7 RX 6 RX 5 RX 4 RX 3 RX 2 RX 1 SCK SEL SELAP 0 SEL SELAP 1 RX 0 data sampled Figure 159 SPI S...

Page 426: ...lly in the non FIFO mode or when the RX FIFO data length is less than the RX FIFO threshold level set in the RXFTLS field Time Out Flag TO The time out function is only available in the SPI FIFO mode and is disabled by loading a zero value into the TOC field in the Time Out Counter register The timeout counter will start counting if the SPI RX FIFO is not empty once data is read from the SPIDR reg...

Page 427: ... SPICR0 register is reset This disables the SPI interface and blocks all output signals from the device 3 The MODE bit in the SPICR1 register is reset This forces the device into slave mode Table 48 SPI Master Mode SEL Pin Status SEL as Input SELOEN 0 SEL as Output SELOEN 1 Multi master Support Not support SPI SEL control signal Use Another GPIO to replace the SEL pin function SEL pin in hardware ...

Page 428: ... As a result the latest received data will be lost The FIFOEN bit in the SPIFCR register is set The read overrun flag is set to indicate that the RX shift register and the RX FIFO are both full if one more data is received This means that the latest received data can not be shifted into the SPI shift register As a result the latest received data will be lost Slave Abort SA In the SPI slave mode th...

Page 429: ... 0 Bits Field Descriptions 15 12 SELHT Chip Select Hold Time 0x0 1 2 SCK 0x1 1 SCK 0x2 3 2 SCK 0x3 2 SCK Note that SELHT is for master mode only 11 8 GUADT Guard Time GUADTEN 1 0x0 1 SCK 0x1 2 SCK 0x2 3 SCK Note that GUADT is for master mode only 7 GUADTEN Guard Time Enable 0 Guard Time is 1 2 SCK 1 When this bit is set Guard time can be controlled by GUADT Note that GUADTEN is for master mode onl...

Page 430: ...LM bit is cleared to 0 for controlling the SEL signal by software Otherwise the SSELC bit has no effect 3 SELOEN Slave Select Output Enable 0 Set the SEL signal to the input mode for multi master mode 1 Set the SEL signal to the output mode for slave select The SELOEN is only available in the master mode to setup the SEL signal as an input or output signal When the SEL signal is configured to oper...

Page 431: ...ave Mode 0 Slave mode 1 Master mode 13 SELM Slave Select Mode 0 SEL signal is controlled by software asserted or de asserted by the SSELC bit 1 SEL signal is controlled by hardware generated automatically by the SPI hardware Note that the SELM bit is available for master mode only MODE 1 12 FIRSTBIT LSB or MSB Transmitted First 0 MSB is transmitted first 1 LSB is transmitted first 11 SELAP Slave S...

Page 432: ...x008 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 TOIEN SAIEN MFIEN ROIEN WCIEN RXBNEIEN TXEIEN TXBEIEN Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 TOIEN Time Out Interrupt Enable 0 Disable 1 Enable 6 SAIEN Slave Abort Interrupt Enable 0 Disa...

Page 433: ...y interrupt request will be generated when the TXBE flag and the TXBEIEN bit are set In the FIFO mode the interrupt request being generated depends upon the TX FIFO trigger level setting SPI Clock Prescaler Register SPICPR This register specifies the SPI clock prescaler ratio Offset 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Rese...

Page 434: ...5 14 13 12 11 10 9 8 DR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 DR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 DR Data Register The SPI data register is used to store the serial bus transmitted or received data In the non FIFO mode writing data into the SPI data register will also load the data into the data transmission buffer known a...

Page 435: ...t empty In the slave mode this flag is set when SEL changes to an active level and is reset when SEL changes to an inactive level 7 TO Time Out flag 0 No RX FIFO time out 1 RX FIFO time out has occurred Write 1 to clear it Once the timeout counter value is equal to the TOC field setting in the SPIFTOCR register the time out flag will be set and an interrupt will be generated if the TOIEN bit in th...

Page 436: ... has been reached in the FIFO mode This bit will be cleared when the SPI RX buffer is empty in the non FIFO mode or if the number of data contained in RX FIFO is less than the trigger level which is specified by the RXFTLS field in the SPIFCR register in the SPI FIFO mode 1 TXE Transmission Register Empty flag 0 TX buffer or TX shift register is not empty 1 TX buffer and TX shift register both are...

Page 437: ...able 0 FIFO disable 1 FIFO enable This bit cannot be set or reset when the SPI interface is in transmitting 7 4 RXFTLS RX FIFO Trigger Level Select 0000 Trigger level is 0 0001 Trigger level is 1 1000 Trigger level is 8 Others Reserved The RXFTLS field is used to specify the RX FIFO trigger level When the number of data contained in the RX FIFO is equal to or greater than the trigger level defined...

Page 438: ...7 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 RXFS TXFS Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 7 4 RXFS RX FIFO Status 0000 RX FIFO empty 0001 RX FIFO contains 1 data 1000 RX FIFO contains 8 data Others Reserved 3 0 TXFS TX FIFO Status 0000 TX FIFO empty 0001 TX FIFO contains ...

Page 439: ... timeout counter starts to count from 0 after the SPI RX FIFO receives a data and reset the counter value once the data is read from the SPIDR register by software or another new data is received If the FIFO does not receive new data or the software does not read data from the SPIDR register the timeout counter value will continuously increase When the timeout counter value is equal to the TOC set...

Page 440: ...ludes an 8 byte transmit FIFO TX FIFO and an 8 byte receive FIFO RX FIFO Software can detect a USART error status by reading USART Status Interrupt Flag Register USRSIFR The status includes the condition of the transfer operations as well as several error conditions resulting from Parity Overrun Framing and Break events The USART includes a programmable baud rate generator which is capable of divi...

Page 441: ...ion Parity overrun and frame error FIFO Receive FIFO 8 9 bits max 9 data bits Transmit FIFO 8 9 bits max 9 data bits Functional Descriptions Serial Data Format The USART module performs a parallel to serial conversion on data that is written to the transmit FIFO registers and then sends the data with the following format Start bit 7 9 LSB MSB first data bits optional Parity bit and finally 1 2 Sto...

Page 442: ...1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity Bit WLS 1 0 b00 PBE 0 WLS 1 0 b01 PBE 0 WLS 1 0 b00 PBE 1 WLS 1 0 b10 PBE 0 WLS 1 0 b01 PBE 1 Figure 163 USART Serial Data Format Baud Rate Generation The baud rate for the USART receiver and transmitter are both set with the same values The baud rate divisor BRD has the following relationship with the USART clock which is known as CK_ USART Baud Rate Clock C...

Page 443: ...tion Error Rate 1 2 4 2 4 4167 0 01 2 9 6 9 6 1042 0 03 3 19 2 19 2 521 0 03 4 57 6 57 6 174 0 22 5 115 2 114 9 87 0 22 6 230 4 232 6 43 0 94 7 460 8 454 5 22 1 36 8 625 625 16 0 Hardware Flow Control The USART supports the hardware flow control function which is enabled by setting the HFCEN bit in the USRCR register to 1 It is possible to control the serial data flow between 2 USART devices by us...

Page 444: ...nput signal If the USART CTS pin is forced to a logic low state the URTXEN bit will automatically be set to 1 to enable the data transmission However if the USART CTS pin is forced to a logic high state the URTXEN bit will be cleared to 0 and then the data transmission will also be disabled When the USART CTS pin is forced to a logic high state during a data transmission period the current data tr...

Page 445: ...g edge is detected on the receiver pin the counter stops counting and is reloaded with the IrDAPSC value When a low pulse falling edge on the receiver pin is detected and then before the debounce filter has counted down to zero a rising edge is also detected then this low pulse will be considered as glitch noise and will be discarded If a low pulse falling edge appears on the receiver pin but no r...

Page 446: ...emodulation IrDAEN 1 RX_Data TX_Data 0 1 0 TX RX SEL SEL TXSEL Figure 169 USART I O and IrDA Block Diagram RS485 Mode The RS485 mode of the USART provides the data transmission on the interface transmitted over a 2 wire twisted pair bus The RS485 transceiver interprets the voltage levels of the differential signals with respect to a third common voltage Without this common reference the transceive...

Page 447: ...ardless of the URRXEN value in the USRCR register all the received data with a parity bit 0 will be ignored until the first address byte is detected with a parity bit 1 and then the received address byte will be stored in the RX FIFO Once the first address data is detected and stored in the RX FIFO the RSADD flag in the USRSIFR register will be set and generate an interrupt if the RSADDIE bit in t...

Page 448: ...le in the USART Synchronous Master Mode i e data transmission and reception both occur at the same time and only support master mode The USART CTS pin is the synchronous USART transmitter clock output In this mode no clock pulses will be sent to the CTS pin during the start bit parity bit and stop bit duration The CPS bit in the Synchronous Control Register SYNCR can be used to determine whether d...

Page 449: ... D0 D1 D2 D3 D4 D5 D6 Parity Start Stop USART TX From Master to Slave USART RX From Slave to Master Clock CPO 0 Clock CPO 1 CPS 1 WLS 1 0 b00 PBE 1 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Start Stop USART TX From Master to Slave USART RX From Slave to Master Clock CPO 0 Clock CPO 1 CPS 0 WLS 1 0 b01 PBE 0 D0 D1 D2 D3 D4 D5 D6 Parity D0 D1 D2 D3 D4 D5 D6 Parity Start Stop USART TX From Mast...

Page 450: ...An interrupt will be generated when the Transmit FIFO is empty and the content of the transmit shift register TSR is also completely shifted Receive FIFO threshold level interrupt An interrupt will be generated when the FIFO received data amount has reached the specified threshold level Register Map The following table shows the USART registers and reset values Table 52 USART Register Map Register...

Page 451: ...s 8 0 DB Reading data via this receiver buffer register will return the data from the receive FIFO The receive FIFO has a capacity of up to 8 9 bits By reading this register the USART will return a 7 8 and 9 bit received data The DB field bit 8 is valid for 9 bit mode only and is fixed at 0 for the 8 bit mode For the 7 bits mode the DB 6 0 field contains the available bits Writing data to this buf...

Page 452: ...e pin status that is controlled by hardware flow control function 14 BCB Break Control Bit When this bit is set 1 the serial data output on the USART TX pin will be forced to the Spacing State logic 0 This bit acts only on USART TX output pin and has no effect on the transmitter logic 13 SPE Stick Parity Enable 0 Disable stick parity 1 Stick Parity bit is transmitted This bit is only available whe...

Page 453: ...generated when 8 bit and 9 bit word length is selected 9 8 WLS Word Length Select 00 7 bits 01 8 bits 10 9 bits 11 Reserved 5 URRXEN USART RX Enable 0 Disable 1 Enable 4 URTXEN USART TX Enable 0 Disable 1 Enable 3 HFCEN Hardware Flow Control Function Enable 0 Disable 1 Enable 2 TRSM Transfer Mode Selection This bit is used to select the data transfer protocol 0 LSB first 1 MSB first 1 0 MODE USART...

Page 454: ... The RXFS field shows the current number of data contained in the RX FIFO 0000 RX FIFO is empty 0001 RX FIFO contains 1 data 1000 RX FIFO contains 8 data Others Reserved 19 16 TXFS TX FIFO Status The TXFS field shows the current number of data contained in the TX FIFO 0000 TX FIFO is empty 0001 TX FIFO contains 1 data 1000 TX FIFO contains 8 data Others Reserved 7 6 RXTL RX FIFO Threshold Level Se...

Page 455: ... 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved CTSIE RXTOIE Type Reset RW 0 RW 0 7 6 5 4 3 2 1 0 RSADDIE BIE FEIE PEIE OEIE TXCIE TXDEIE RXDRIE Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 9 CTSIE CTS Clear To Send Interrupt Enable 0 Disable interrupt 1 Enable interrupt If this bit is set an interrupt will be generated when the CTSC bit is set in the ...

Page 456: ... OEIE Overrun Error Interrupt Enable 0 Disable interrupt 1 Enable interrupt If this bit is set an interrupt will be generated when the OEI bit is set in the USRSIFR register 2 TXCIE Transmit Complete Interrupt Enable 0 Disable interrupt 1 Enable interrupt If this bit is set an interrupt will be generated when the TXC bit is set in the USRSIFR register 1 TXDEIE Transmit Data Empty Interrupt Enable ...

Page 457: ...iting 1 to this bit clears the flag 9 RSADD RS485 Address Detection 0 Address is not detected 1 Address is detected This bit will be set to 1 when the receiver detects the address An interrupt will be generated if RSADDIE 1 in the USRIER register Writing 1 to this bit clears the flag Note This bit is only used in the RS485 mode by setting the MODE field in the USRCR register 8 TXC Transmit Complet...

Page 458: ...he spacing state logic 0 for longer than a full word transmission time which is the total time of start bit data bits parity stop bits duration Writing 1 to this bit clears the flag 3 FEI Framing Error Indicator This bit will be set to 1 whenever the received character does not have a valid stop bit which means the stop bit following the last data bit or parity bit is detected as a logic 0 Writing...

Page 459: ...ransmitter time guard counter is driven by the baud rate clock When the TX FIFO transmits data the counter will be reset and then starts to count after a word transmission has completed Only when the counter content is equal to the TG value are further word transmission transactions allowed 7 RXTOEN Receive FIFO Time Out Counter Enable 0 Receive FIFO Time Out Counter is disabled 1 Receive FIFO Tim...

Page 460: ...e USART clock named as CK_ USART The counting period is specified by the IrDAPSC field The IrDAPSC field must be set to a value equal to or greater than 0x01 for normal debounce counter operation If the pulse width is less than the duration specified by the IrDAPSC field the pulse will be considered as glitch noise and discarded 00000000 Reserved can not be used 00000001 CK_USART clock divided by ...

Page 461: ...6 Reserved Type Reset 15 14 13 12 11 10 9 8 ADDMATCH Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved RSAAD RSNMM TXENP Type Reset RW 0 RW 0 RW 0 Bits Field Descriptions 15 8 ADDMATCH RS485 Auto Address Match value The field contains the address match value for the RS485 auto address detection operation mode 2 RSAAD RS485 Auto Address Detection Operation Mode Control 0 D...

Page 462: ... 0 RW 0 Bits Field Descriptions 3 CPO Clock Polarity 0 CTS SCK pin idle state is low 1 CTS SCK pin idle state is high Selects the polarity of the clock output on the USART CTS SCK pin in the synchronous mode Works in conjunction with the CPS bit to specify the desired clock idle state 2 CPS Clock Phase 0 Data is captured on the first clock edge 1 Data is captured on the second clock edge This bit ...

Page 463: ...e 0x0000_0010 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 BRD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 BRD Type Reset RW 0 RW 0 RW 0 RW 1 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 BRD Baud Rate Divider The 16 bits define the USART clock divider ratio Baud Rate CK_USART BRD Where the CK_USART clock is...

Page 464: ...ister controls the USART debug mode Offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved LBM Type Reset RW 0 RW 0 Bits Field Descriptions 1 0 LBM Loopback Test Mode Select 00 Normal Operation 01 Reserved 10 Automatic Echo Mode 11 Loopback Mode ...

Page 465: ...ister TSR and a receive data register RDR and receive shift register RSR Software can detect a UART error status by reading the UART Status Interrupt Flag Register URSIFR The status includes the condition of the transfer operations as well as several error conditions resulting from Parity Overrun Framing and Break events The UART includes a programmable baud rate generator which is capable of divi...

Page 466: ...dle state The Stop bit is the same as the data line idle state and provides a delay before the next start situation Both the Start and Stop bits are used for data synchronization during the asynchronous data transmission The UART module also performs a serial to parallel conversion on the data that is read from the receive data register It will first check the Parity bit and will then look for a S...

Page 467: ...K_UART clock is the APB clock connected to the UART while the BRD range is from 16 to 65535 CK_UART BRD 18 Reference Divisor Clock Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bitn Parity Bit Stop Bit Next Start Bit n 6 8 Figure 175 UART Clock CK_UART and Data Frame Timing Table 53 Baud Rate Deviation Error Calculation CK_UART 20 MHz Baud Rate CK_UART 20 MHz No Kbps Actual BRD Deviation Error Rate 1 2 4 2 4...

Page 468: ...egister empty interrupt An interrupt is generated when the content of the transmit data register is transferred to the transmit shift register TSR Transmit complete interrupt An interrupt is generated when the transmit data register TDR is empty and the content of the transmit shift register TSR is also completely shifted Receive data ready interrupt An interrupt is generated when the content of t...

Page 469: ... 9 8 Reserved DB Type Reset RW 0 7 6 5 4 3 2 1 0 DB Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 8 0 DB By reading this register the UART will return a 7 8 and 9 bit received data The DB field bit 8 is valid for the 9 bit mode only and is fixed at 0 for the 8 bit mode For the 7 bit mode the DB 6 0 contains the available bits By writing to this register the UART will s...

Page 470: ...1 Stick Parity bit is transmitted This bit is only available when the PBE bit is set to 1 If both the PBE and SPE bits are set to 1 and the EPE bit is cleared to 0 the transmitted parity bit will be stuck to 1 However when the PBE and SPE bits are set to 1 and also the EPE bit is set to 1 the transmitted parity bit will be stuck to 0 12 EPE Even Parity Enable 0 Odd number of logic 1 s are transmit...

Page 471: ...24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved BIE FEIE PEIE OEIE TXCIE TXDEIE RXDRIE Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 6 BIE Break Interrupt Enable 0 Disable interrupt 1 Enable interrupt If this bit is set an interrupt is generated when the break interrupt is enabled and the ...

Page 472: ...led and the TXDE bit is set in the URSIFR register 0 RXDRIE Receive Data Ready Interrupt Enable 0 Disable interrupt 1 Enable interrupt If this bit is set an interrupt is generated when the receive data ready interrupt is enabled and the RXDR bit is set in the URSIFR register UART Status Interrupt Flag Register URSIFR This register contains the corresponding UART status Offset 0x010 Reset value 0x0...

Page 473: ...ut is held in the spacing state logic 0 for longer than a full character transmission time which is the total time of start bit data bits parity stop bits duration Writing 1 to this bit clears the flag 3 FEI Framing Error Indicator This bit is set 1 whenever the received character does not have a valid stop bit which means the stop bit following the last data bit or parity bit is detected as logic...

Page 474: ...024 Reset value 0x0000_0010 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 BRD Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 BRD Type Reset RW 0 RW 0 RW 0 RW 1 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 15 0 BRD Baud Rate Divider The 16 bits define the UART clock divider ratio Baud Rate CK_UART BRD Where the CK_UA...

Page 475: ...ontrols the UART debug mode Offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved LBM Type Reset RW 0 RW 0 Bits Field Descriptions 1 0 LBM Loopback Test Mode Select 00 Normal Operation 01 Reserved 10 Automatic Echo Mode 11 Loopback Mode ...

Page 476: ...scriptions The division and modulus functions of the truncated division are related in the following way A B Q R Where A is Dividend B is Divisor Q is Quotient and R is Remainder The divider requires a software trigger start signal to start a calculation by setting the START bit in the Divider Control Register The divider calculation complete flag will be set to 1 after 8 clock cycles however if t...

Page 477: ... Reset value 0x0000_0008 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 Reserved COM ZEF Reserved START Type Reset RO 1 RO 0 RW 0 Bits Field Descriptions 3 COM Calculation Complete Flag 0 Data is invalid 1 New data is valid If this bit is set to 1 it indicates that the divider calculation is complete...

Page 478: ... RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 31 0 DDR Dividend Data Register This bit field is used to specify the dividend of the divider calculation Divisor Data Register DSR The register is used to specify the divisor data Offset 0x008 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 DSR Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 23 22 21 20 19 18 17 16 DSR Type Reset RW 0 RW 0 RW 0 RW 0...

Page 479: ...0 RO 0 RO 0 Bits Field Descriptions 31 0 QTR Quotient Data Register This bit field is used to store the quotient of the divider calculation result Remainder Data Register RMR The register is used to store the remainder data Offset 0x010 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 RMR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RMR Type Reset RO 0 RO 0 RO 0 RO 0 R...

Page 480: ...ibed above If the new CRC code result does not match the one calculated earlier that means data stream contains a data error CRC Control Register CRC Seed Register B3 B2 B1 B0 MUX 1 s COMP BIT REVERSE CCITT 16 POLY CRC 16 POLY CRC 32 POLY MUX MUX CRC REG 1 s COMP BIT REVERSE BYTE REVERSE CRC FSM AHB Bus CRC Data Register CRC Sum Register BYTE REVERSE Figure 177 CRC Block Diagram Features Supports ...

Page 481: ...ata width 4 AHB clock cycles for 32 bit data input 2 AHB clock cycles for 16 bit data input 1 AHB clock cycle for 8 bit data input Byte and Bit Reversal for CRC Computation The byte reordering and byte level bit reversal operation can be occurred before the data is used in the CRC calculation or after the CRC checksum output They are configurable using the corresponding setting field of the CRCCR ...

Page 482: ...fies the corresponding CRC function enable control Offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 Reserved Type Reset 23 22 21 20 19 18 17 16 Reserved Type Reset 15 14 13 12 11 10 9 8 Reserved Type Reset 7 6 5 4 3 2 1 0 SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV DATBIRV POLY Type Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Bits Field Descriptions 7 SUMCMPL 1 s Complement operation on ...

Page 483: ... to specify the CRC seed Offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 SEED Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 31 0...

Page 484: ... RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 CHKSUM Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 CHKSUM Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 CHKSUM Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bits Field Descriptions 31 0 CHKSUM CRC Checksum Data Get the CRC 16 32 bit checksum result through this register according to the polynom...

Page 485: ...A Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 CRCDATA Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 CRCDATA Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 CRCDATA Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 Bits Field Descriptions 31 0 CRCDATA CRC Input Data Byte half word and word writes are allowed 1 s complemen...

Page 486: ...re used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek re...

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