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Rev. 1.00
350 of 486
July 31, 2018
32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
16 Motor Control T
imer (MCTM)
16 Motor Control T
imer (MCTM)
Bits
Field
Descriptions
[8][2:0]
CH2OM[3:0] Channel 2 Output Mode Setting
These bits define the functional types of the output reference signal CH2OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH2OREF is forced to 0
0101: Force active – CH2OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 2 has an active level when CNTR <
CH2CCR or otherwise has an inactive level.
- During down-counting, channel 2 has an inactive level when CNTR >
CH2CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 2 has an inactive level when CNTR <
CH2CCR or otherwise has an active level.
- During down-counting, channel 2 has an active level when CNTR >
CH2CCR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 2 has an active level when CNTR <
CH2CCR or otherwise has an inactive level.
- During down-counting, channel 2 has an inactive level when CNTR >
CH2ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 2 has an inactive level when CNTR <
CH2CCR or otherwise has an active level.
- During down-counting, channel 2 has an active level when CNTR >
CH2ACR or otherwise has an inactive level
Note: When channel 2 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Center-
aligned Counting mode (CMSEL = 0x1 / 0x2 / 0x3).