GE Medical Systems marquette Dash 2000, Service Manual, Page: 44 / 202

EQUIPMENT OVERVIEW: Theory of Operation
2-22 DASH 2000 Patient Monitor Revision A
2000 412-001
PCB Functions The main processor PCB is essentially a self-contained, single-board
computer. It includes a Motorola MPC821 microcontroller functioning as
the host processor. The MPC821 has an integrated graphics system
controller handling the video interface. The system application code is
stored in electrically erasable FLASH memory for easy software updates.
Data memory is implemented with static RAM (SRAM), all of which is
backed with a gold capacitor.
Because of the large number of memory and peripheral devices which are
interfaced to the MPC821, a multiple bus structure is employed. This
approach limits the number of devices sharing a given bus and results in
increased reliability and lower system noise. It allows most devices to
operate at (or near) full speed because the capacitance each device I/O
sees is typically no more than 100 pF.
To keep the overall size of the board to a minimum, the design utilizes a
high-density Field Programmable Gate Array device (FPGAs). One of the
outstanding features of this board is the almost total lack of Small Scale
Integration (SSI) logic devices (gates, counters, etc.). Functions which
required SSI devices in the past are now implemented in the FPGAs.
These devices, which we referr to as ASICs (Application Specific
Integrated Circuits) in this theory of operation, handle such functions as
main system control, bus interface, NBP interface and the writer, and
keypad interface. The ASIC is implemented using Altera Flex 6000
devices which must be loaded with a logic program each time the system
powers up.
MPC821 High Integration
Microcontroller
The Motorola MPC821 microcontroller was chosen as the main (host)
processor for the monitor. This chip allows it to run existing Tram and
Solar software, along with numerous on-chip peripherals such as a
Universal Asynchronous Receiver Transmitter (SCC/SMC) and Serial
Peripheral Interface (SPI). It also incorporates a very sophisticated Time
Processing Unit (TPU) which is only utilized to a very small extent on
the processor PCB. A special feature is the integrated graphic system
controller which handles the complete video interface. An additional
support feature of the MPC821 is the Background Debug Mode (BDM)
which allows testing of the board (a special connector is incorporated on
the edge of the board to access this mode).
The monitor actually utilizes a 821 on the main board and a 68332 on the
acquisition PCB (DAS). The two processors communicate over the
isolation barrier using the on-chip SPI. This interface operates at up to
4 megabits per second, transfers packets of up to 256 bits without CPU
intervention, and requires very little external interface hardware. The
Main (host) Processor functions as the SPI master in this design.
Basic Initialization
Requirements Because of the numerous on-chip peripheral registers, the 821 requires
many configuration steps before it becomes fully operational in the
system. In addition, certain basic steps are required by the hardware
design and must be performed immediately upon power-up.