GE Medical Systems marquette Dash 2000, Service Manual, Page: 41 / 202

EQUIPMENT OVERVIEW: Theory of Operation
Revision A DASH 2000 Patient Monitor 2-19
2000 412-001
opto-isolators and associated circuitry. The programmable queue allows
the QSPI to perform up to sixteen (bytes) serial transfers without CPU
intervention.
The MC68332 QSPI is designed to be used in a multiprocessor
environment where one processor is the master and the other processors
are slaves. A signal generated from the master processor selects the
QSPI slave mode for the DAS processor which enables communications.
During normal operation, the DAS processor is a slave to the MPC821
host processor on the main processor PCB. Upon power up or reset, the
DAS processor is designed to come up in the Background Debug Mode
(BDM) since no boot code resides on the DAS. Direct communication with
BDM allows the master to execute a number of commands including
loading boot code into the memory if the DAS has never been
programmed. Logic then disconnects the BDM communication link so the
SPI link is connected directly between the host processor and the DAS
processor. The host processor can then download the executable program
into the FLASH memory.
The memory configuration is two 128K x 8 FLASH chips and direct
addressing of two 128K x 8 static RAM chips. The RAM is expandable by
moving zero-ohm jumpers if using higher density RAM chips.
The CMOS FLASH memory uses a high-integration block architecture.
Programming of one block does not affect data stored in another block,
allowing maximum flexibility.
The DAS control ASIC is a multifunction digital interface which provides
logic interface support for the MC68332 processor. The ASIC provides the
following functions:
¥ A latched buffer for analog to digital conversion,
¥ Provides logic to enable processor BDM upon power up or reset;
connects serial communications to the processor debug module,
¥ The communication interface and control to the pulse oximetry
function, and
¥ Identification for the ASIC and circuit board.
Isolated Power Supply
The voltage monitor for both isolated sections is an under-voltage
sensing circuit which generates a reset to the processor if the 5-volt
isolated supply voltage drops below 4.6 VDC.
The isolated power supply for both isolated sections is a current mode
control flyback converter providing a main +5-volt regulated output
(digital supply), a ±5 volts, as well as a ±12 volt winding cross regulated
output (analog supplies). To achieve UL 544 patient connected hi-pot
and leakage requirements, a specially designed potted coupled inductor
and optical isolation are used. The supply uses feedback loss time-out for
overload protection.
Calibration The calibration procedure for the this assembly is found in Chapter 5,
ÒCalibrationÓ.