c )
REV.-A
Memory Write Timing
The memory write timing consists of three states, T1 to
Timings for address output and the ALE signal are the same as those for the memory read machine
cycle, however,
to O
to O) are not disabled after the memory address is output, and write
data is output on
to O from the beginning of T2 to the end of
The WR signal is output from
the middle of T1 to the beginning of
CLOCK
AB15 -8
-O)
x
ADDRESS
x
-o
-O)
ADDRESS
x x
WRITE DATA
x
NOTE:
Figure A-9. Memory Write Timing
When
to O and
to O are output to the mautiplexed address/data bus
to O) and
address bus (AB 15 to 7), both the
and WR signals during the machine cycle are HIGH when
external memory is not being accessed.
A-1 1
Summary of Contents for LQ-2550
Page 1: ...L Q 2 5 5 0 TECHNICAL MANUAL EPSON ...
Page 240: ...REV A P r cl Figure 6 3 LQ 2550 Lubrication and Adhesive Application Points Diagram 2 6 3 ...
Page 241: ...REV A 7 i_ Figure 6 4 LQ 2550 Lubrication and Adhesive Application Points Diagram 3 6 4 ...
Page 252: ...REV A I 1 I 7 v m o m x b Figure A 6 PPD781OHG Block Diagram A 7 ...
Page 297: ...REV A 1 L I Irl N I i t 1 I I x Figure A 50 ROPSE Board Circuit Diagram A 52 ...
