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REV.-A
2.3.8 PG and CS Motors Control/Drive Circuits
Figure 2-89 shows a block diagram of the PG motor and CS motor drive
(3B) is mapped
into the sub CPU address space, and the PG and
motors are controlled from the sub CPU by sending
commands to the
(3
reference clock required to generate phase switching pulses for the
stepper motor drive is generated by the timer within the sub CPU, which generates the phase switching
pulses for the PG and CS motor drive circuits by sending commands to the
The PG and CS motors are driven using constant voltage.
PG
MOTOR
Cs
MOTOR
+ 3 5 + 5
I
1
HOLD\ DRIVE
c
PG MOTOR
DRIVER
CIRCUIT
PHASE PULSES
1
I
GH
+35 +5
A
A
A
I
I
1
HOLD/DRIVE
MOTOR
c
DRIVER
CIRCUIT
PHASE PULSES
(CS UNIT)
I
AO1
DO1
ADO
1
3
MSU
(3 B)
D02
ADDRESS
PF6
1
( 6 A )
7
ALE
SUB CPU
LOW ADDRESS
PDO
(7 B)
LATCH (8A)
1
7
c
I
GH
L
.
Figure 2-89. PG and
Motors Drive Circuits Block Diagram
2-98
Summary of Contents for LQ-2550
Page 1: ...L Q 2 5 5 0 TECHNICAL MANUAL EPSON ...
Page 240: ...REV A P r cl Figure 6 3 LQ 2550 Lubrication and Adhesive Application Points Diagram 2 6 3 ...
Page 241: ...REV A 7 i_ Figure 6 4 LQ 2550 Lubrication and Adhesive Application Points Diagram 3 6 4 ...
Page 252: ...REV A I 1 I 7 v m o m x b Figure A 6 PPD781OHG Block Diagram A 7 ...
Page 297: ...REV A 1 L I Irl N I i t 1 I I x Figure A 50 ROPSE Board Circuit Diagram A 52 ...