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2.3.7.2 CR Motor Control/Drive Circuit
The circuits included in the CR motor control/drive circuit are as follows.
Clock Generation Circuit
Figure 2-78 shows the TM 1 clock generation circuit and Figure 2-79 shows the timing for the sub CPU
output signal and TM 1 signal. This circuit employs
LS 123 (5A). This
generates the
TM 1 signal that includes a constant LOW pulse width even when the frequency of the reference clock
output from the TO terminal of the sub CPU changes (when acceleration, deceleration, or constant speed
control is performed.) The LOW pulse width is set to approximately 25
by R25 and C 13.
NOTE: In the
SUE
CPU
(78)
MCU \
+5
Figure 2-78.
Clock Generation Circuit
TO
pin
pin
draft sel
f
test mode:
= 254
T2 = 123
Figure 2-79. Sub CPU Output Signal and
Signal T
T3= 2
[/4s]
2-84
Summary of Contents for LQ-2550
Page 1: ...L Q 2 5 5 0 TECHNICAL MANUAL EPSON ...
Page 240: ...REV A P r cl Figure 6 3 LQ 2550 Lubrication and Adhesive Application Points Diagram 2 6 3 ...
Page 241: ...REV A 7 i_ Figure 6 4 LQ 2550 Lubrication and Adhesive Application Points Diagram 3 6 4 ...
Page 252: ...REV A I 1 I 7 v m o m x b Figure A 6 PPD781OHG Block Diagram A 7 ...
Page 297: ...REV A 1 L I Irl N I i t 1 I I x Figure A 50 ROPSE Board Circuit Diagram A 52 ...