Cypress CY8C28 series, Technical Reference Manual

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312 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
Digital Register Summary
The following table lists all the PSoC registers for the digital system in address order (Add. column) within their system
resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written
with a value of ‘0’. The naming conventions for the digital row registers and the digital block registers are detailed in their
respective table title rows.
Note that all PSoC devices with a base part number of CY8C28xxx fall into one of the following categories with respect to their
digital PSoC rows: 3 row device or 2 row device. The “PSoC Digital System Block Diagram” at the beginning of this section
illustrates this.
In the following table, the third column from the left titled “Digital Rows” indicates which of the two PSoC device categories the
register falls into. To determine the number of digital rows in your PSoC device, refer to the table titled
“PSoC Device Charac-
teristics” on page 311 .
Summary Table of the Digital Registers
Add. Name
Digital
Rows
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
GLOBAL DIGITAL INTERCONNECT (GDI) REGISTERS (page 322 )
1,A0h
GDI_O_IN_CR
3, 2, GDIOICR7 GDIOICR6 GDIOICR5 GDIOICR4 GDIOICR3 GDIOICR2 GDIOICR1 GDIOICR0 RW : 00
1,A1h
GDI_E_IN_CR
3, 2, GDIEICR7 GDIEICR6 GDIEICR5 GDIEICR4 GDIEICR3 GDIEICR2 GDIEICR1 GDIEICR0 RW : 00
1,A2h
GDI_O_OU_CR
3, 2, GDIOOCR7 GDIOOCR6 GDIOOCR5 GDIOOCR4 GDIOOCR3 GDIOOCR2 GDIOOCR1 GDIOOCR0 RW : 00
1,A3h
GDI_E_OU_CR
3, 2, GDIEOCR7 GDIEOCR6 GDIEOCR5 GDIEOCR4 GDIEOCR3 GDIEOCR2 GDIEOCR1 GDIEOCR0 RW : 00
1,D0h GDI_O_IN 3, 2, GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 RW : 00
1,D1h GDI_E_IN 3, 2, GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 RW : 00
1,D2h GDI_O_OU 3, 2, GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW : 00
1,D3h GDI_E_OU 3, 2, GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOEUTIN1 GOEUTIN0 RW : 00
DIGITAL ROW REGISTERS (page 329 )
x,B0h RDI0RI 3, 2, RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00
x,B1h RDI0SYN 3, 2, RI3SYN RI2SYN RI1SYN RI0SYN RW : 00
x,B2h RDI0IS 3, 2, BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00
x,B3h RDI0LT0 3, 2, LUT1[3:0] LUT0[3:0] RW : 00
x,B4h RDI0LT1 3, 2, LUT3[3:0] LUT2[3:0] RW : 00
x,B5h RDI0RO0 3, 2, GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00
x,B6h RDI0RO1 3, 2, GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00
x,B7h RDI0DSM 3, 2, AVG_SEL[3:0] AVG_EN[3:0] RW : 00
x,B8h RDI1RI 3, 2, RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00
x,B9h RDI1SYN 3, 2, RI3SYN RI2SYN RI1SYN RI0SYN RW : 00
x,BAh RDI1IS 3, 2, BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00
x,BBh RDI1LT0 3, 2, LUT1[3:0] LUT0[3:0] RW : 00
x,BCh RDI1LT1 3, 2, LUT3[3:0] LUT2[3:0] RW : 00
x,BDh RDI1RO0 3, 2, GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00
x,BEh RDI1RO1 3, 2, GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00
x,BFh RDI1DSM 3, 2, AVG_SEL[3:0] AVG_EN[3:0] RW : 00
x,C0h RDI2RI 3 RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00
x,C1h RDI2SYN 3 RI3SYN RI2SYN RI1SYN RI0SYN RW : 00
x,C2h RDI2IS 3 BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00
x,C3h RDI2LT0 3 LUT1[3:0] LUT0[3:0] RW : 00
x,C4h RDI2LT1 3 LUT3[3:0] LUT2[3:0] RW : 00
x,C5h RDI2RO0 3 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00
x,C6h RDI2RO1 3 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00
x,C7h RDI2DSM 3 AVG_SEL[3:0] AVG_EN[3:0] RW : 00