CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
181
RDIxIS
x,B2h
13.2.52
RDIxIS
Row Digital Interconnect Input Select Register
This register is used to configure the inputs to the digital row LUTS and select a broadcast driver from another row if present.
The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your
PSoC device (see the table titled
“PSoC Device Characteristics” on page 311
), some addresses may not be available. In the
table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should
always be written with a value of ‘0’. For additional information, refer to the
“Register Definitions” on page 329
in the Row Dig-
ital Interconnect chapter
.
5:4
BCSEL[1:0]
When the BCSEL value is equal to the row number, the
buffer that drives the row broadcast
from the input select mux is disabled, so that one of the row’s blocks may drive the local row
broadcast net.
00b
Row 0 drives row broadcast net.
01b
Row 1 drives row broadcast net.
10b
Row 2 drives row broadcast net. Reserved for 2 row PSoC devices.
11b
Row 3 drives row broadcast net. Reserved for 2 row PSoC devices.
3
IS3
0
The ‘A’ input of LUT3 is RO[3].
1
The ‘A’ input of LUT3 is RI[3].
2
IS2
0
The ‘A’ input of LUT2 is RO[2].
1
The ‘A’ input of LUT2 is RI[2].
1
IS1
0
The ‘A’ input of LUT1 is RO[1].
1
The ‘A’ input of LUT1 is RI[1].
0
IS0
0
The ‘A’ input of LUT0 is RO[0].
1
The ‘A’ input of LUT0 is RI[0].
Individual Register Names and Addresses:
x,B2h
RDI0IS : x,B2h
RDI1IS : x,BAh
RDI2IS : x,C2h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
BCSEL[1:0]
IS3
IS2
IS1
IS0
Bit
Name
Description
Summary of Contents for CY8C28 series
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