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Cypress CY8C28 series, Technical Reference Manual

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CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G

I

2

C

28.3.3

I2Cx_SCR Register 

The I

2

C Status and Control Register (I2C_SCR) is used by

both master and slave to control the flow of data bytes and
to keep track of the bus state during a transfer.

This register contains status bits, for determining the state of

the current I

2

C transfer, and control bits, for determining the

actions for the next byte transfer. At the end of each byte

transfer, the I

2

C hardware interrupts the M8C microcon-

troller and stalls the I

2

C bus on the subsequent low of the

clock, until the PSoC device intervenes with the next com-
mand. This register may be read as many times as neces-
sary; but on a subsequent write to this register, the bus stall
is released and the current transfer will continue. 

There are six status bits: Byte Complete, LRB, Address,
Stop Status, Lost Arb, and Bus Error. These bits have Read/
Clear (R/C) access, which means that they are set by hard-
ware but may be cleared by a write of ‘0’ to the bit position.
Under certain conditions, status is cleared automatically by
the hardware. These cases are noted in 

Table 28-5

.

There are two control bits: Transmit and ACK. These bits
have RW access and may be cleared by hardware.

Bit 7: Bus Error.  

The Bus Error status detects misplaced

Start or Stop conditions on the bus. These may be due to
noise, rogue devices, or other devices that are not yet syn-

chronized with the I

2

C bus traffic. According to the I

2

C spec-

ification, all compatible devices must reset their interface on
a received Start or Stop. This is a natural thing to do in Slave
mode, because a Start will initiate an address reception and
a Stop will idle the slave. In the case of a master, this event
will force the master to release the bus and idle. However,
because a master does not respond to external Start or Stop
conditions, an immediate interrupt on this event allows the
master to continue to keep track of the bus state.

A bus error is defined as follows. A Start is only valid if the
block is idle (master or slave) or a Slave receiver is ready to
receive the first bit of a new byte after an ACK. Any other
timing for a Start condition causes the Bus Error bit to be set.
A Stop is only valid if the block is idle or a Slave receiver is
ready to receive the first bit of a new byte after an ACK. Any
other timing for a Stop condition causes the Bus Error bit to
be set. 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Access

0,xxh

I2Cx_SCR

Bus Error

Lost Arb

Stop 

Status

ACK

Address

Transmit

LRB

Byte 

Complete

# : 00

LEGEND

# Access is bit specific. Refer to 

Table 28-5

 for detailed bit descriptions.

Xx An “x” in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,

refer to the 

“System Resources Register Summary” on page 462

.

Note

 2nd I

2

C block in CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 devices only.

Table 28-5.  I2C_SCR Status and Control Register

Bit

Access

Description

Mode

7

RC

Bus Error

1 = A misplaced Start or Stop condition was 
detected.

This status bit must be cleared by firmware with 
a write of ‘0’ to the bit position. It is never 
cleared by the hardware.

Master 
Only

6

RC

Lost Arb

1 = Lost Arbitration.

This bit is set immediately on lost arbitration; 
however, it does not cause an interrupt. This 
status may be checked after the following Byte 
Complete interrupt.

Any Start detect will automatically clear this bit.

Master 
Only

5

RC

Stop Status

1 = A Stop condition was detected.

This status bit must be cleared by firmware with 
a write of ‘0’ to the bit position. It is never 
cleared by the hardware.

Master/
Slave

4

RW

ACK: Acknowledge Out

0 = NAK the last received byte.

1 = ACK the last received byte.

This bit is automatically cleared by hardware 
on the following Byte Complete event. 

Master/
Slave

3

RC

Address

1 = The transmitted or received byte is an 
address.

This status bit must be cleared by firmware with 
a write of ‘0’ to the bit position.

Master/
Slave

2

RW

Transmit

0 = Receive Mode.

1 = Transmit Mode.

This bit is set by firmware to define the direc-
tion of the byte transfer. 

Any Start detect will automatically clear this bit.

Master/
Slave

1

RC

LRB: Last Received Bit

The value of the ninth bit in a Transmit 
sequence, which is the acknowledge bit from 
the receiver.

 0 = Last transmitted byte was ACKed by the 
receiver.

1 = Last transmitted byte was NAKed by the 
receiver.

Any Start detect will automatically clear this bit.

Master/
Slave

0

RC

Byte Complete

Transmit Mode: 

1 = 8 bits of data have been transmitted and an 
ACK or NAK has been received.

Receive Mode: 

1 = 8 bits of data have been received.

Any Start detect will automatically clear this bit.

Master/
Slave

Summary of Contents for CY8C28 series

Page 1: ...ers as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document Future revisions will occur when appropriate and any changes will be set out on the document history page Continuity of ordering part numbers Infineon continues to support existing pa...

Page 2: ...ogrammable System on Chip TRM Technical Reference Manual Document No 001 52594 Rev G January 20 2017 Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 800 858 1810 Phone Intnl 408 943 2600 http www cypress com ...

Page 3: ...F MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR POSE To the extent permitted by applicable law Cypress reserves the right to make changes to this document without fur ther notice Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or prog...

Page 4: ...ction C Register Reference 109 13 Register Details 125 Section D Digital System 311 14 Global Digital Interconnect GDI 317 15 Array Digital Interconnect ADI 325 16 Row Digital Interconnect RDI 327 17 Digital Blocks 335 Section E Analog System 383 18 Analog Interface 393 19 Analog Array 409 20 Analog Input Configuration 417 21 Analog Reference 421 22 Continuous Time PSoC Block 425 23 Switched Capac...

Page 5: ... Overview iv CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G 33 I O Analog Multiplexer 525 34 Real Time Clock RTC 533 35 10 Bit SAR ADC Controller 537 Section H Glossary 545 Index 561 ...

Page 6: ...Conventions 27 Numeric Naming 27 Units of Measure 27 Acronyms 28 1 Pin Information 29 1 1 Pinouts for the CY8C28xxx 29 1 1 1 20 Pin Part Pinouts 30 1 1 2 28 Pin Part Pinouts 31 1 1 3 44 Pin Part Pinouts 32 1 1 4 48 Pin Part Pinouts 33 1 1 5 56 Pin Part Pinout 34 Section B PSoC Core 35 Top Level Core Architecture 35 Interpreting the Core Documentation 35 Core Register Summary 36 2 CPU Core M8C 39 2...

Page 7: ... HWBootReset Function 51 3 1 2 3 ReadBlock Function 51 3 1 2 4 WriteBlock Function 52 3 1 2 5 EraseBlock Function 52 3 1 2 6 ProtectBlock Function 52 3 1 2 7 TableRead Function 52 3 1 2 8 EraseAll Function 53 3 1 2 9 Checksum Function 53 3 1 2 10 Calibrate0 Function 53 3 1 2 11 Calibrate1 Function 53 3 1 2 12 WriteAndVerify Function 54 3 2 Register Definitions 54 3 2 1 FLS_PR1 Register 54 3 2 2 Re...

Page 8: ...ster 70 5 3 2 4 INT_MSK1 Register 71 5 3 3 INT_VC Register 71 5 3 4 CPU_F Register 72 6 General Purpose I O GPIO 73 6 1 Architectural Description 73 6 1 1 Digital I O 73 6 1 2 Global I O 73 6 1 3 Analog Input 74 6 1 4 GPIO Block Interrupts 75 6 2 Register Definitions 76 6 2 1 PRTxDR Registers 76 6 2 2 PRTxIE Registers 76 6 2 3 PRTxGS Registers 76 6 2 4 PRTxDMx Registers 77 6 2 5 PRTxICx Registers ...

Page 9: ... 12 1 1 32 kHz Clock Selection 97 12 1 2 Sleep Timer 97 12 2 Application Description 98 12 3 Register Definitions 99 12 3 1 INT_MSK0 Register 99 12 3 2 RES_WDT Register 99 12 3 3 CPU_SCR1 Register 100 12 3 4 CPU_SCR0 Register 101 12 3 5 OSC_CR0 Register 102 12 3 6 OSC_CR2 Register 103 12 3 7 ILO_TR Register 103 12 3 8 ECO_TR Register 104 12 4 Timing Diagrams 104 12 4 1 Sleep Sequence 104 12 4 2 Wa...

Page 10: ...125 Register Conventions 126 13 1 1 Register Naming Conventions 126 13 2 Bank 0 Registers 127 13 2 1 PRTxDR 127 13 2 2 PRTxIE 128 13 2 3 PRTxGS 129 13 2 4 PRTxDM2 130 13 2 5 DxCxxDR0 131 13 2 6 DxCxxDR1 132 13 2 7 DxCxxDR2 133 13 2 8 DxCxxCR0 Timer Control 000 134 13 2 9 DxCxxCR0 Counter Control 001 135 13 2 10 DxCxxCR0 Dead Band Control 100 136 13 2 11 DxCxxCR0 CRCPRS Control 010 137 13 2 12 DxCx...

Page 11: ...IxSYN 180 13 2 52 RDIxIS 181 13 2 53 RDIxLT0 182 13 2 54 RDIxLT1 184 13 2 55 RDIxRO0 186 13 2 56 RDIxRO1 187 13 2 57 RDIxDSM 188 13 2 58 CUR_PP 189 13 2 59 STK_PP 190 13 2 60 IDX_PP 191 13 2 61 MVR_PP 192 13 2 62 MVW_PP 193 13 2 63 I2Cx_CFG 194 13 2 64 I2Cx_SCR 195 13 2 65 I2Cx_DR 197 13 2 66 I2Cx_MSCR 198 13 2 67 INT_CLR0 199 13 2 68 INT_CLR1 201 13 2 69 INT_CLR2 203 13 2 70 INT_CLR3 204 13 2 71 ...

Page 12: ...40 13 3 21 CMP_GO_EN1 241 13 3 22 AMD_CR1 242 13 3 23 ALT_CR0 243 13 3 24 ALT_CR1 244 13 3 25 CLK_CR2 245 13 3 26 AMUX_CFG1 246 13 3 27 SADC_TSCR0 247 13 3 28 SADC_TSCR1 248 13 3 29 ACE_AMD_CR0 249 13 3 30 ACE_AMX_IN 250 13 3 31 ACE_CMP_CR0 251 13 3 32 ACE_CMP_CR1 252 13 3 33 ACE_CMP_GI_EN 253 13 3 34 ACE_ALT_CR0 254 13 3 35 ACE_ABF_CR0 255 13 3 36 ACExxCR1 256 13 3 37 ACExxCR2 257 13 3 38 ASExxCR...

Page 13: ..._CR2 298 13 3 79 VLT_CR 299 13 3 80 VLT_CMP 300 13 3 81 ADCx_TR 301 13 3 82 IDAC_MODE 302 13 3 83 IMO_TR 303 13 3 84 ILO_TR 304 13 3 85 BDG_TR 305 13 3 86 ECO_TR 306 13 3 87 IMO_TR1 307 13 3 88 FLS_PR1 308 13 3 89 IDAC_CR0 309 Section D Digital System 311 Top Level Digital Architecture 311 Interpreting the Digital Documentation 311 Digital Register Summary 312 14 Global Digital Interconnect GDI 31...

Page 14: ...ut Data Synchronization 337 17 1 6 Timer Function 337 17 1 6 1 Usability Exceptions 338 17 1 6 2 Block Interrupt 338 17 1 7 Counter Function 338 17 1 7 1 Counter Timing 338 17 1 7 2 Usability Exceptions 339 17 1 7 3 Block Interrupt 339 17 1 8 Dead Band Function 339 17 1 8 1 Usability Exceptions 340 17 1 8 2 Block Interrupt 340 17 1 9 PWMDBL Function 340 17 1 9 1 Usability Exceptions 341 17 1 9 2 B...

Page 15: ...finitions 353 17 2 2 DxCxxCR0 Register 353 17 2 3 DxCxxCR1 Register 357 17 2 4 INT_MSK1 Register 359 17 2 5 DxCxxFN Registers 360 17 2 6 DxCxxIN Registers 361 17 2 7 DxCxxOU Registers 361 17 3 Timing Diagrams 363 17 3 1 Timer Timing 363 17 3 2 Counter Timing 366 17 3 3 Dead Band Timing 367 17 3 3 1 Changing the PWM Duty Cycle 367 17 3 3 2 Kill Operation 368 17 3 4 PWMDBL Timing 369 17 3 5 CRCPRS T...

Page 16: ...R0 Register 404 18 3 8 CLK_CR1 Register 405 18 3 9 AMD_CR0 Register 405 18 3 10 CMP_GO_EN Register 406 18 3 11 CMP_GO_EN1 Register 406 18 3 12 AMD_CR1 Register 407 18 3 13 ALT_CR0 Register 407 18 3 14 ALT_CR1 Register 407 18 3 15 CLK_CR2 Register 408 19 Analog Array 409 19 1 Architectural Description 409 19 1 1 NMux Connections 410 19 1 2 PMux Connections 411 19 1 3 RBotMux Connections 412 19 1 4 ...

Page 17: ...4 1 1 1 Analog Comparator Bus Interface 442 24 1 1 2 Analog Column Clock Generation 442 24 1 1 3 Single Slope ADC 442 24 1 1 4 PWM ADC Interface 444 24 1 1 5 Analog Modulator Interface Mod Bits 444 24 1 1 6 Sample and Hold Feature 444 24 1 2 Analog Array 445 24 1 2 1 NMux Connections 445 24 1 2 2 PMux Connections 446 24 1 2 3 Temperature Sensing Capability 446 24 1 3 Analog Input Configuration 446...

Page 18: ...al Oscillator 467 25 1 4 External Clock 467 25 1 4 1 Clock Doubler 467 25 1 4 2 Switch Operation 467 25 2 Register Definitions 469 25 2 1 INT_CLR0 Register 469 25 2 2 INT_MSK0 Register 469 25 2 3 OSC_GO_EN Register 470 25 2 4 OSC_CR4 Register 471 25 2 5 OSC_CR3 Register 472 25 2 6 OSC_CR0 Register 473 25 2 7 OSC_CR1 Register 474 25 2 8 OSC_CR2 Register 475 26 Multiply Accumulate MAC 477 26 1 Archi...

Page 19: ...on Description 494 28 2 1 Slave Operation 494 28 2 2 Master Operation 496 28 3 Register Definitions 497 28 3 1 I2Cx_ADDR Register 497 28 3 2 I2Cx_CFG Register 498 28 3 3 I2Cx_SCR Register 500 28 3 4 I2Cx_DR Register 502 28 3 5 I2Cx_MSCR Register 502 28 4 PSoC Device Distinctions 504 28 5 Timing Diagrams 504 28 5 1 Clock Generation 504 28 5 2 Basic Input Output Timing 505 28 5 3 Status Timing 505 2...

Page 20: ...r 525 33 1 Architectural Description 525 33 1 1 IOMUX and GPIO 525 33 1 2 Dual Channel 8 Bit IDAC 525 33 2 PSoC Device Distinctions 526 33 3 Application Description 526 33 3 1 Capacitive Sensing 526 33 3 2 Chip Wide Analog Input 528 33 3 3 Crosspoint Switch 528 33 3 4 Charging Current 528 33 4 Register Definitions 528 33 4 1 AMUX_CFG Register 528 33 4 2 IDAC1_D Register 529 33 4 3 IDAC0_D Register...

Page 21: ...ng Bit and Interrupt 540 35 1 7 Converted Data Format and Read Sequence 540 35 2 Application Description 540 35 2 1 ADC Sample Rate and Clock Selection 540 35 2 2 Voltage Doubler Enable 540 35 2 3 Reference Selection 540 35 3 Register Definitions 541 35 3 1 SADC_DH 541 35 3 2 SADC_DL 541 35 3 3 SADC_TSCR0 541 35 3 4 SADC_TSCR1 542 35 3 5 SADC_TSCMPL 542 35 3 6 SADC_TSCMPH 542 35 3 7 SADC_CR0 543 3...

Page 22: ...ithin the sections have an introduction an architectural application description PSoC device dis tinctions if relevant register definitions and timing diagrams The sections are as follows Overview Presents the PSoC top level architecture PSoC device characteristics and distinctions how to get started with helpful information and document history and conventions The PSoC device pinouts are detailed...

Page 23: ...n page 24 This allows you the optimum choice of system resources for your application The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin The buses also allow for signal multiplexing and for perform ing logic operations This configurability frees your designs from the constraints of a fixed peripheral controller Analog System The An...

Page 24: ... Internal Main Oscillator IMO PSoC CORE CPU Core M8C Supervisory ROM SROM Flash Nonvolatile Memory 16K Digital PSoC Block Array Analog PSoC Block Array Analog Ref 2 Multiply Accumulate MACs Switch Mode Pump 2 I2 C Blocks Internal Voltage Reference Digital Clocks POR and LVD System Resets 4 Type 2 Decimators SYSTEM RESOURCES ACC DBC DBC DCC DCC DBC DBC DCC DCC DBC DBC DCC DCC Phase Locked Loop PLL ...

Page 25: ...e lists the resources available for specific CY8C28xxx device groups The check mark or appropriate information denotes that a system resource is available for the device Blank fields indicate that the system resource is not available These resources are detailed in the section titled System Resources on page 461 CY8C28xxx Device Characteristics PSoC Part Number CapSense Digital Blocks Regular Anal...

Page 26: ...urce Availability Some CY8C28xxx groups do not have a second hardware I2 C resource I2C1 The following registers are reserved for these devices I2C1_DR I2C1_SCR I2C1_MSCR I2C1_CFG I2C1_ADDR CY8C28x13 CY8C28x33 CY8C28x52 I2C chapter on page 493 Dedicated 10 bit SAR ADC Availability Some CY8C28xxx groups do not have a dedicated 10 bit SAR ADC The following registers are reserved for these devices SA...

Page 27: ...tware and Driv ers Also provided are critical updates to system documentation under Design Support Design Resources More Resources or go to http www cypress com Development Kits Development Kits are available from the following distributors Digi Key Avnet Arrow and Future The Cypress Online Store contains development kits C compilers and all accessories for PSoC development Go to the Cypress Onlin...

Page 28: ...e b for example 01010100b or 01000011b Numbers not indicated by an h or b are decimal Units of Measure The following table lists the units of measure used in this manual Register Conventions Convention Example Description x in a register name ACCxxCR1 Multiple instances address ranges of the same register R R 00 Read register or bit s W W 00 Write register or bit s L RL 00 Logical register or bit ...

Page 29: ...programming IVR interrupt vector read LFSR linear feedback shift register LRb last received bit LRB last received byte LSb least significant bit LSB least significant byte LUT look up table MISO master in slave out MOSI master out slave in MSb most significant bit MSB most significant byte PC program counter PCH program counter high PCL program counter low PD power down PMA PSoC memory arbiter POR...

Page 30: ...e individual PSoC device s data sheet or go to http www cypress com psoc This chapter encompasses the following Pinouts for the CY8C28xxx on page 29 1 1 Pinouts for the CY8C28xxx The CY8C28xxx PSoC devices are available in a variety of packages Refer to the following information for details on individ ual devices Every port pin labeled with a P except for Vss Vdd and XRES in the following tables a...

Page 31: ...s Ground connection 11 I O M P1 0 Crystal XTALout I2 C Serial Data SDA 12 I O M P1 2 13 I O M P1 4 Optional External Clock Input EXTCLK 14 I O M P1 6 15 Input XRES Active high pin reset with internal pull down 16 I O I M S P0 0 Analog column mux input ADC input chan nel 17 I O I O M S P0 2 Analog column mux input and column output ADC input channel 18 I O I O M S P0 4 Analog column mux input and c...

Page 32: ... and CY8C28x33 devices only have one I2C block Therefore this GPIO does not function as an I2C pin for these devices 17 I O M P1 4 Optional External Clock Input EXT CLK 18 I O M P1 6 I2C1 Serial Clock SCL d 19 Input XRES Active high external reset with internal pull down 20 I O I M P2 0 Direct switched capacitor block inpute e This pin is not a direct switched capacitor block analog input for CY8C...

Page 33: ...ore this pin does not function as an analog column output for these devices 26 Input XRES Active high pin reset with internal pull down 37 I O I O M S P0 4 Analog column mux and SAR ADC input Analog column outputb c 27 I O M P4 0 38 I O I M S P0 6 Analog column mux and SAR ADC inputb 28 I O M P4 2 39 Power Vdd Supply voltage 29 I O M P4 4 40 I O I M S P0 7 Analog column mux and SAR ADC inputb 30 I...

Page 34: ...ADC input Analog column outputc e 32 I O M P4 4 46 I O I M S P0 1 Analog column mux input ADC input channel 33 I O M P4 6 47 I O M P2 7 34 I O I M P2 0 Direct switched capacitor block inputf 48 I O M P2 5 35 I O I M P2 2 Direct switched capacitor block inputf LEGEND A Analog I Input O Output S SAR ADC Input and M Analog Mux Bus Input These are the ISSP pins which are not High Z at POR Power On Res...

Page 35: ... connection 46 I O M P4 4 30 NC No connection 47 I O M P4 6 31 I O M P1 0 Crystal Output XTALout I2C0 Serial Data SDA ISSP SDATA 48 I O I M P2 0 Direct switched capacitor block input 32 I O M P1 2 I2C1 Serial Data SDA 49 I O I M P2 2 Direct switched capacitor block input 33 I O M P1 4 Optional External Clock Input EXT CLK 50 I O M P2 4 External Analog Ground AGND 34 I O M P1 6 I2C1 Serial Clock SC...

Page 36: ...e PSoC device s core Each component of the figure is dis cussed at length in this section PSoC Core Block Diagram Interpreting the Core Documentation The core section covers the heart of the PSoC device which includes the M8C microcontroller SROM interrupt con troller GPIO analog output drivers and SRAM paging mul tiple clock sources such as IMO ILO ECO and PLL and sleep and watchdog functionality...

Page 37: ...D1h STK_PP Page Bits 2 0 RW 00 0 D4h MVR_PP Page Bits 2 0 RW 00 0 D5h MVW_PP Page Bits 2 0 RW 00 x FEh CPU_SCR1 IRESS SLIMO ECO EXW ECO EX IRAMDIS 00 1 FAh FLS_PR1 Bank RW 00 RAM PAGING SRAM REGISTERS page 60 x 6Ch TMP_DRx Data 7 0 RW 00 x 6Dh TMP_DR1 Data 7 0 RW 00 x 6Eh TMP_DR2 Data 7 0 RW 00 x 6Fh TMP_DR3 Data 7 0 RW 00 0 D0h CUR_PP Page Bits 2 0 RW 00 0 D1h STK_PP Page Bits 2 0 RW 00 0 D3h IDX...

Page 38: ...e Mode 1 7 0 RW FFh 1 0Eh PRT3IC0 Interrupt Control 0 7 0 RW 00 1 0Fh PRT3IC1 Interrupt Control 1 7 0 RW 00 0 10h PRT4DR Data 7 0 RW 00 0 11h PRT4IE Interrupt Enables 7 0 RW 00 0 12h PRT4GS Global Select 7 0 RW 00 0 13h PRT4DM2 Drive Mode 2 7 0 RW FFh 1 10h PRT4DM0 Drive Mode 0 7 0 RW 00 1 11h PRT4DM1 Drive Mode 1 7 0 RW FFh 1 12h PRT4IC0 Interrupt Control 0 7 0 RW 00 1 13h PRT4IC1 Interrupt Contr...

Page 39: ...EN D WDR32_SE EXTCLKEN RSVD SYSCLKX2 DIS RW 00 1 E9h ILO_TR Bias Trim 1 0 Freq Trim 3 0 W 00 1 EBh ECO_TR PSSDC 1 0 W 00 LEGEND L The and f expr or f expr and xor f expr instructions can be used to modify this register Access is bit specific Refer to the Register Details chapter on page 125 for additional information X The value for power on reset is unknown x An x before the comma in the address ...

Page 40: ...nted so that it always points to the next stack byte in RAM If the last byte in the stack is at address FFh the stack pointer will wrap to RAM address 00h It is the firmware developer s responsibility to ensure that the stack does not overlap with user defined variables in RAM With the exception of the F register the M8C internal regis ters are not accessible via an explicit register address The i...

Page 41: ...r 6A 4 1 RLC A C Z 11 4 2 SUB A expr C Z 3E 10 2 MVI A expr Z 6B 7 2 RLC expr C Z 12 6 2 SUB A expr C Z 3F 10 2 MVI expr A 6C 8 2 RLC X expr C Z 13 7 2 SUB A X expr C Z 40 4 1 NOP 6D 4 1 RRC A C Z 14 7 2 SUB expr A C Z 41 9 3 AND reg expr expr Z 6E 7 2 RRC expr C Z 15 8 2 SUB X expr A C Z 42 10 3 AND reg X expr expr Z 6F 8 2 RRC X expr C Z 16 9 3 SUB expr expr C Z 43 9 3 OR reg expr expr Z 70 4 2 ...

Page 42: ...X expr 11 4 2 SUB A expr C Z 70 4 2 AND F expr C Z 5A 5 2 MOV expr X 12 6 2 SUB A expr C Z 41 9 3 AND reg expr expr Z 5B 4 1 MOV A X Z 13 7 2 SUB A X expr C Z 42 10 3 AND reg X expr expr Z 5C 4 1 MOV X A 14 7 2 SUB expr A C Z 64 4 1 ASL A C Z 5D 6 2 MOV A reg expr Z 15 8 2 SUB X expr A C Z 65 7 2 ASL expr C Z 5E 7 2 MOV A reg X expr Z 16 9 3 SUB expr expr C Z 66 8 2 ASL X expr C Z 5F 10 3 MOV expr...

Page 43: ... address FFh CPU_SCR register The final category for one byte instructions are those that cause updates of the internal M8C registers This category holds the largest number of instructions ASL ASR CPL DEC INC MOV POP RET RETI RLC ROMX RRC SWAP These instructions can cause the A X and SP regis ters or SRAM to update 2 5 2 Two Byte Instructions The majority of M8C instructions are two bytes in lengt...

Page 44: ...urce address in RAM The following is an example of this instruction MOV 7 5 2 6 Addressing Modes The M8C has ten addressing modes These modes are detailed and located on the following pages Source Immediate on page 43 Source Direct on page 44 Source Indexed on page 44 Destination Direct on page 45 Destination Indexed on page 45 Destination Direct Source Immediate on page 45 Destination Indexed Sou...

Page 45: ...the signed offset to determine the address of the source value in RAM or register address space The result of these instructions is placed in either the M8C A or X register as indicated by the instruction s opcode All instructions using the Source Indexed addressing mode are two bytes in length Source Indexed Examples Table 2 7 Source Direct Opcode Operand 1 Instruction Source Address Source Code ...

Page 46: ...nd 2 of the instruction All instructions using the Destination Direct Source Immediate addressing mode are three bytes in length Destination Direct Source Immediate Examples Table 2 9 Destination Direct Opcode Operand 1 Instruction Destination Address Source Code Machine Code Comments ADD 7 A 04 07 The value in the Accumulator is added to memory at address 7 The result is placed in memory at addre...

Page 47: ...ource address is stored in operand 2 of the instruction The instruction using the Destination Direct Source Direct addressing mode is three bytes in length Destination Direct Source Direct Example Table 2 12 Destination Indexed Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Index Immediate Value Source Code Machine Code Comments ADD X 7 5 07 07 05 The value in memory at addres...

Page 48: ...here the Accumulator s value is stored The pointer s value is incremented after the value is written to the destination address For PSoC microcontrollers with more than 256 bytes of RAM the Data Page Write MVW_PP register is used to determine which RAM page to use with the destination address Therefore values can be stored in pages other than the current page without changing the Current Page Poin...

Page 49: ...configuration space Bit 2 Carry The Carry flag bit is set or cleared in response to the result of several instructions It can also be manipu lated by the flag logic opcodes for example OR F 4 See the PSoC Designer Assembly Guide User Manual for more details Bit 1 Zero The Zero flag bit is set or cleared in response to the result of several instructions It can also be manipu lated by the flag logic...

Page 50: ...he MVR_PP and the MVW_PP pointers are not disabled by clearing the CPU_F PgMode bits Therefore the POINTER parameter is interpreted as an address in the page indicated by the MVI page pointers when the supervi sory operation is called This allows the data buffer used in the supervisory operation to be located in any SRAM page See the RAM Paging chapter on page 57 for more details regarding the MVR...

Page 51: ...ruction with an accumulator value of 00h If the checksum of the calibration data is valid the SWBootReset function ends by setting the internal M8C reg isters to 00h writing 00h to most SRAM addresses in SRAM Page 0 and then begins to execute user code at address 0000h See Table 3 4 and the following paragraphs for more information on which SRAM addresses are modified If the checksum is not valid ...

Page 52: ...le If read protection is turned on the ReadBlock function exits setting the accumulator and KEY2 back to 00h KEY1 has a value of 01h indicating a read failure If read protection is not enabled the function reads 64 bytes from the Flash using a ROMX instruction and stores the results in SRAM using an MVI instruction The 64 bytes are stored in SRAM beginning at the address indicated by the value of ...

Page 53: ...r and KEY2 back to 00h KEY1 has a value of 01h indicating a write failure To set up the parameter block for the EraseBlock function store the correct key values in KEY1 and KEY2 The block number to erased must be stored in the BLOCKID variable and the CLOCK and DELAY values must be set based on the current CPU speed For more information on setting the CLOCK and DELAY values see Clocking Strategy o...

Page 54: ...that flash bank For example if the BLOCKID is equal to 150 the function calculates the checksum for block 0 to block 127 and again for block 0 to block 21 The 16 bit checksum is returned in KEY1 and KEY2 The parameter KEY1 holds the lower 8 bits of the checksum and the parameter KEY2 holds the upper 8 bits of the checksum 3 1 2 10 Calibrate0 Function The Calibrate0 function transfers the calibrati...

Page 55: ... the section titled TableRead Function on page 52 3 1 2 12 WriteAndVerify Function The WriteAndVerify function works exactly the same as the WriteBlock function with one exception When the write operation has completed the SROM will then read back the contents of Flash and compare those values against the val ues in SRAM thus verifying that the write was successful The write and verify is one SROM...

Page 56: ...sh bank the SROM Flash functions should operate on The default value for the Bank bit is zero Flash bank 0 holds up to the first 8K of user code as well as the cal table The optional Flash bank 1 holds additional user code For additional information refer to the FLS_PR1 register on page 308 3 2 2 Related Registers STK_PP Register on page 61 MVR_PP Register on page 61 MVW_PP Register on page 62 CPU...

Page 57: ...CK value can be calculated the values for M B and Mult must be determined These are device spe cific values that are stored in the Flash Table 3 and are accessed by way of the TableRead SROM function see the TableRead Function on page 52 If the operating tempera ture is at or below 0 C use the cold values For operating temperatures at or above 0 C use the hot values See Table 3 11 for more informa...

Page 58: ...n tage of the additional SRAM pages The memory paging architecture consists of five areas Stack Operations Interrupts MVI Instructions Current Page Pointer Indexed Memory Page Pointer The first three of these areas have no dependency on the CPU_F register s PgMode bits and are covered in the next subsections after Basic Paging The function of the last two depend on the CPU_F PgMode bits and will b...

Page 59: ...e code will start execu tion in SRAM Page 0 If it is necessary for the ISR to change to another SRAM page it can be accomplished by changing the values of the CPU_F 7 6 bits to enable the special SRAM addressing modes However any change made to the CUR_PP IDX_PP or STK_PP registers will persist after the ISR returns Therefore the ISR should save the current value of any paging register it modifies...

Page 60: ...tically enabled when an interrupt occurs in a PSoC device and is therefore considered the default ISR mode This is because before the ISR is entered the M8C pushes the current value of the CPU_F register on to the stack and then clears the CPU_F register Therefore by default any indexed memory access in an ISR is guaranteed to occur in SRAM Page 0 When the RETI instruction is executed to end the I...

Page 61: ...DRx registers refer to the Summary Table of the Core Registers on page 36 For additional information refer to the TMP_DRx register on page 155 4 2 2 CUR_PP Register The Current Page Pointer Register CUR_PP is used to set the effective SRAM page for normal memory accesses in a multi SRAM page PSoC device Bits 2 to 0 Page Bits 2 0 These bits affect the SRAM page that is accessed by an instruction wh...

Page 62: ...on indexed address modes to operate on an SRAM page that is not equal to the current SRAM page However the effect this register has on indexed addressing modes is only enabled when the CPU_F 7 6 is set to 10b When CPU_F 7 6 is set to 10b and an indexed memory access is made the access is directed to the SRAM page indicated by the value of the IDX_PP register See the STK_PP register description for...

Page 63: ...space accessed when the XIO bit is set to 0 is called the user space while the address space accessed when the XIO bit is set to 1 is called the configuration space Bit 2 Carry The Carry Flag bit is set or cleared in response to the result of several instructions It can also be manipulated by the flag logic opcodes for example OR F 4 See the PSoC Designer Assembly Guide User Manual for more detail...

Page 64: ... bit is used to select the register bank that is active for a register read or write This bit allows the PSoC device to have 512 8 bit registers and therefore can be thought of as the ninth address bit for registers The address space accessed when the XIO bit is set to 0 is called the user space while the address space accessed when the XIO bit is set to 1 is called the configuration space Bit 2 C...

Page 65: ...64 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G RAM Paging ...

Page 66: ... 1 An interrupt becomes active either because a the interrupt condition occurs for example a timer expires b a previously posted interrupt is enabled through an update of an interrupt mask register or c an interrupt is pending and GIE is set from 0 to 1 in the CPU Flag register 2 The current executing instruction finishes 3 The internal interrupt routine executes taking 13 cycles During this time ...

Page 67: ...he interrupts only come into consideration if more than one interrupt is pending dur ing the same instruction cycle In this case the priority encoder see Figure 5 1 generates an interrupt vector for the highest priority interrupt that is pending 5 1 1 Posted versus Pending Interrupts An interrupt is posted when its interrupt conditions occur This results in the flip flop in Figure 5 1 clocking in ...

Page 68: ...te hardware system necessary to generate a real interrupt The following table lists the interrupts for all CY8C28xxx devices and the priorities that are available in each CY8C28xxx device Table 5 1 Device Interrupts and Priorities Interrupt Priority Interrupt Address CY8C28x03 CY8C28x13 CY8C28x23 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52 Interrupt Name 0 Highest 0000h Reset 1 0004h Supply Voltage Mo...

Page 69: ... is cleared will cause the corresponding interrupt to clear If the ENSWINT bit is set any 0 s written to the INT_CLRx registers are ignored However 1 s written to an INT_CLRx register while ENSWINT is set will cause an interrupt to post for the corre sponding interrupt Note When using the INT_CLRx register to post an inter rupt the hardware interrupt source such as a digital clock must not have it...

Page 70: ...lows posted DBC00 interrupts to be read cleared or set for row 0 block 0 For additional information refer to the INT_CLR1 register on page 201 5 3 1 3 INT_CLR2 Register Bit 3 DCC23 This bit allows posted DCC23 interrupts to be read cleared or set for row 2 block 3 Bit 2 DCC22 This bit allows posted DCC22 interrupts to be read cleared or set for row 2 block 2 Bit 1 DBC21 This bit allows posted DBC2...

Page 71: ...ed or set Bit 2 SARADC This bit allows posted SARADC interrupts to be read masked or set Bit 1 I2C1 This bit allows posted I2C1 interrupts to be read masked or set Bit 0 I2C0 This bit allows posted I2C0 interrupts to be read masked or set For additional information refer to the INT_MSK3 register on page 206 5 3 2 2 INT_MSK2 Register Depending on the digital row characteristics of your PSoC device ...

Page 72: ...masked or set for row 0 block 0 For additional information refer to the INT_MSK1 register on page 209 5 3 3 INT_VC Register The Interrupt Vector Clear Register INT_VC returns the next pending interrupt and clears all pending interrupts when written Bits 7 to 0 Pending Interrupt 7 0 When the register is read the least significant byte LSB of the highest prior ity pending interrupt is returned For e...

Page 73: ... cleared by the user using the flag logic instructions for example OR F 1 GIE is also cleared automatically by the M8C upon entering the interrupt service routine ISR after the flag byte has been stored on the stack preventing nested interrupts Note that the bit can be set in an ISR if desired For GIE 1 the M8C samples the IRQ input for each instruction For GIE 0 the M8C ignores the IRQ For additi...

Page 74: ...the GPIO ports is to allow the M8C to send information out of the PSoC device and get information into the M8C from outside the PSoC device This is accomplished by way of the port data register PRTxDR Writes from the M8C to the PRTxDR register store the data state one bit per GPIO In the standard non bypass mode the pin drivers drive the pin in response to this data bit with a drive strength deter...

Page 75: ...lock For analog modes the GPIO block is typically configured into a High impedance Analog Drive mode High Z The mode turns off the Schmitt trigger on the input path which may reduce power consumption and decrease internal switching noise when using a particular I O as an analog input Refer to the Electrical Specifications chapter in the individual PSoC device data sheet Figure 6 1 GPIO Block Diagr...

Page 76: ... the GPIO pin transitions if not already transitioned appropri ately high or low to match the interrupt mode configuration When this happens the INTO line will pull low to assert the GPIO interrupt This assumes the other system level enables are on such as setting the global GPIO interrupt enable and the Global Interrupt Enable Setting the pin inter rupt enable may immediately assert INTO if the I...

Page 77: ...O block Bits 7 to 0 Interrupt Enables 7 0 A 1 enables the INTO output at the block and a 0 disables INTO so it is only High Z For additional information refer to the PRTxIE register on page 128 6 2 3 PRTxGS Registers The Port Global Select Register PRTxGS is used to select the block for connection to global inputs or outputs Bits 7 to 0 Global Select 7 0 Writing this register high enables the glob...

Page 78: ...h DC drive strength Mode 101b gives the same drive strength but with slower edges The open drain modes 100b and 111b also use the slower edge rate drive These modes enable open drain functions such as I2C mode 111b although the slow edge rate is not slow enough to meet the I2 C fast mode specification For additional information refer to the PRTxDM2 register on page 130 the PRTxDM0 register on page...

Page 79: ...t enable line is set high This mode switches between low mode and high mode depending on the last value that was read from the port during reads of the data register PRTxDR If the last value read from the GPIO was 0 the GPIO will subsequently be in Interrupt High mode If the last value read from the GPIO was 1 the GPIO will then be in Interrupt Low mode Figure 6 3 GPIO Interrupt Mode 11b Figure 6 ...

Page 80: ...s will match the number of analog columns in a device The user must select no more than one analog block per column to drive a signal on its analog output bus ABUS to serve as the input to the ana log driver for that column The output from the analog output driver for each column can be enabled and disabled using the Analog Output Driver register ABF_CR0 If the analog output driver is enabled then...

Page 81: ...pter on page 417 Bit 7 ACol1MUX A mux selects the output of column 0 input mux or column 1 input mux When set this bit sets the column 1 input to column 0 input mux output Bit 6 ACol2MUX A mux selects the output of column 2 input mux or column 3 input mux When set this bit sets the column 2 input to column 3 input mux output Bits 5 to 2 ABUFxEN These bits enable or disable the column output amplif...

Page 82: ... available by setting the slow IMO SLIMO bit in the CPU_SCR1 register With this bit set and the corresponding factory trim value applied to the IMO_TR register SYSCLK can be lowered to 6 MHz This offers lower device power consumption for sys tems that can operate with the reduced system clock Slow IMO mode is discussed further in the Application Descrip tion on page 81 8 2 Application Description ...

Page 83: ...it to indicate that the ECO EX bit has been previ ously written to It is read only When this bit is a 1 this indi cates that the CPU_SCR1 register has been written to and is now locked When this bit is a 0 the register has not been written to since the last reset event Bit 2 ECO EX The ECO Exists bit serves as a flag to the hardware to indicate that an external crystal oscillator exists in the sys...

Page 84: ...3 IMO_TR Register The Internal Main Oscillator Trim Register IMO_TR is used to manually center the oscillator s output to a target fre quency The PSoC device specific value for 5 V operation is loaded into the Internal Main Oscillator Trim register IMO_TR at boot time The Internal Main Oscillator will operate within specified tolerance over a voltage range of 4 75 V to 5 25 V with no modification ...

Page 85: ...84 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Internal Main Oscillator IMO ...

Page 86: ...egister table showing the bit structure The bits in the table that are grayed out are reserved bits and are not detailed in the register description that follows Note that reserved bits should always be written with a value of 0 9 2 1 ILO_TR Register The Internal Low Speed Oscillator Trim Register ILO_TR sets the adjustment for the internal low speed oscillator The device specific value placed in ...

Page 87: ...86 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Internal Low Speed Oscillator ILO ...

Page 88: ...o the ILO immedi ately The ECO Exists bit ECO EX bit 2 in the CPU_SCR1 regis ter is used to control whether the switch over is allowed or locked This is a write once bit It is written early in code exe cution after a Power On Reset POR or external reset XRES event A 1 in this bit indicates to the hardware that a crystal exists in the system and firmware is allowed to switch back and forth between ...

Page 89: ...ons that require accuracy on the 32 kHz clock should be enabled after the transition in oscillator domains 10 1 1 ECO External Components The external component connections and selections of the External Crystal Oscillator are illustrated in Figure 10 2 Crystal 32 768 kHz watch crystal such as Epson C 002RX Capacitors C1 C2 use NPO ceramic caps Use the following equation if you do not employ PLL m...

Page 90: ... 6 MHz The IMO trim value must also be changed when SLIMO is set see Engaging Slow IMO on page 81 When not in external clocking mode the IMO is the source for SYSCLK there fore when the speed of the IMO changes so will SYSCLK Bit 3 ECO EXW The ECO Exists Written bit is used as a status bit to indicate that the ECO EX bit has been previ ously written to It is read only When this bit is a 1 this ind...

Page 91: ...ements to be tailored to the application The reset value for the CPU Speed bits is zero therefore the default CPU speed is one eighth of the clock source The Internal Main Oscillator IMO is the default clock source for the CPU speed circuit therefore the default CPU speed is 3 MHz The CPU frequency is changed with a write to the OSC_CR0 register There are eight frequencies generated from a power o...

Page 92: ... or the crystal oscillator are synchronized to this clock source If an external clock is enabled PLL mode should be off The external clock input is located on port P1 4 When using this input the pin drive mode should be set to High Z not High Z analog Bit 1 RSVD Reserved bit This bit should always be 0 Bit 0 SYSCLKX2DIS When set the Internal Main Oscilla tor s doubler is disabled This results in a...

Page 93: ...92 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G External Crystal Oscillator ECO ...

Page 94: ...se the jitter on the out put If longer lock time is tolerable the PLLGAIN bit can be held high all the time After the 32 768 kHz External Crystal Oscillator ECO has been selected and enabled the following procedure should be followed to enable the PLL and allow for proper fre quency lock Select a CPU frequency of 3 MHz or less Enable the PLL Wait between 10 and 50 ms depending on bit 7 of the OSC_...

Page 95: ...ght frequencies generated from a power of 2 divide circuit which are selected by a 3 bit code At any given time the CPU 8 to 1 clock mux is selecting one of the available frequencies which is resyn chronized to the 24 MHz master clock at the output Regardless of the CPU Speed bit s setting if the actual CPU speed is greater than 12 MHz the 24 MHz operating requirements apply An example of this sce...

Page 96: ...CLKEN bit is set the external clock becomes the source for the internal clock tree SYSCLK which drives most PSoC device clocking functions All external and internal signals including the 32 kHz clock whether derived from the Internal Low Speed Oscillator ILO or the crystal oscillator are synchronized to this clock source If an external clock is enabled PLL mode should be off The external clock inp...

Page 97: ...96 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Phase Locked Loop PLL ...

Page 98: ...lly or from the 32 kHz clock are examples of asynchronous interrupts that can also be used to wake the system up The Watchdog Timer WDT circuit is designed to assert a hardware reset to the device after a pre programmed inter val unless it is periodically serviced in firmware In the event that an unexpected execution path is taken through the code this functionality serves to reboot the system It ...

Page 99: ...ed as soon as the device enters Sleep mode the Sleep bit is cleared by the pending interrupt and Sleep mode is exited immediately Note 3 On wakeup the instruction immediately after the sleep instruction is executed before the interrupt service rou tine if enabled The instruction after the sleep instruction is pre fetched before the system actually goes to sleep Therefore when an interrupt occurs t...

Page 100: ... This bit controls the sleep interrupt enable For additional information refer to the INT_MSK0 register on page 208 12 3 2 RES_WDT Register The Reset Watchdog Timer Register RES_WDT is used to clear the watchdog timer a write of any value and clear both the watchdog timer and the sleep timer a write of 38h Bits 7 to 0 WDSL_Clear 7 0 The Watchdog Timer WDT write only register is designed to timeout...

Page 101: ...a status bit to indicate that the ECO EX bit has been previ ously written to It is read only When this bit is a 1 this indi cates that the CPU_SCR1 register has been written to and is now locked When this bit is a 0 the register has not been written to since the last reset event Bit 2 ECO EX The ECO Exists bit serves as a flag to the hardware to indicate that an external crystal oscillator exists ...

Page 102: ... Sleep mode when set To wake up the system this register bit is cleared asynchronously by any enabled interrupt There are two special features of this register bit that ensures proper Sleep operation First the write to set the register bit is blocked if an interrupt is about to be taken on that instruction boundary immediately after the write Sec ond there is a hardware interlock to ensure that wh...

Page 103: ... be tailored to the application The reset value for the CPU Speed bits is zero therefore the default CPU speed is one eighth of the clock source The Internal Main Oscillator IMO is the default clock source for the CPU speed circuit therefore the default CPU speed is 3 MHz The CPU frequency is changed with a write to the OSC_CR0 register There are eight frequencies generated from a power of 2 divid...

Page 104: ... drive mode should be set to High Z not High Z analog Bit 1 RSVD Reserved bit This bit should always be 0 Bit 0 SYSCLKX2DIS When set the Internal Main Oscilla tor s doubler is disabled This results in a reduction of overall device power on the order of 1 mA It is advised that any application that does not require this doubled clock should have it turned off For additional information refer to the ...

Page 105: ...bit in the CPU_SCR0 register The Bus Request BRQ signal to the CPU is immedi ately asserted This is a request by the system to halt CPU operation at an instruction boundary 2 The CPU issues a Bus Request Acknowledge BRA on the following positive edge of the CPU clock 3 The sleep logic waits for the following negative edge of the CPU clock and then asserts a system wide Power Down PD signal In Figu...

Page 106: ... interrupt occurs and is synchronized by the negative edge of the 32 kHz clock 2 At the following positive edge of the 32 kHz clock the system wide PD signal is negated The Flash memory module IMO and bandgap any POR LVD circuits are all powered up to a normal operating state 3 At the next positive edge of the 32 kHz clock the values of the bandgap are settled and sampled 4 At the following negati...

Page 107: ...2 2 Wakeup Sequence CLK32K INT SLEEP PD CPUCLK 24 Mhz BRQ BRA CPU Sleep timer or GPIO interrupt occurs CPU is restarted after 75 s nominal Not to Scale BANDGAP LVD PPOR ENABLE POR LVD BANDGAP SAMPLE BANDGAP Interrupt is double sampled by 32K clock and PD is negated to system SAMPLE LVD POR LVD PPOR is valid ...

Page 108: ...de after a POR or XRES all code should be written as if it is enabled that is the WDT should be cleared period ically This is because in the initialization code after a WDR event the watchdog timer is enabled so all code must be aware of this The watchdog timer is three counts of the sleep timer inter rupt output The watchdog interval is three times the selected sleep timer interval The available ...

Page 109: ...nsumption Sleep mode power consumption consists of the items in the following tables In Table 12 5 the typical block currents shown do not repre sent maximums These currents do not include any analog block currents that may be on during Sleep mode While the CLK32K can be turned off in Sleep mode this mode is not useful because it makes it impossible to restart unless an imprecise power on reset IP...

Page 110: ...13CR3 is a register for an analog PSoC block in row 1 column 3 Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is also referred to as I O space and is broken into two parts The XIO bit in the Flag register CPU_F determines which bank the user is currently in When the XIO bit is set the user is said to be in the extended address space or th...

Page 111: ...D 9D INT_CLR3 DD RW 204 1E 5E 9E INT_MSK3 DE RW 206 1F 5F 9F INT_MSK2 DF RW 207 DBC00DR0 20 131 60 A0 INT_MSK0 E0 RW 208 DBC00DR1 21 W 132 61 A1 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 62 A2 INT_VC E2 RC 210 DBC00CR0 23 134 63 A3 RES_WDT E3 W 211 DBC01DR0 24 131 64 A4 I2C1_SCR E4 195 DBC01DR1 25 W 132 65 A5 I2C1_MSCR E5 198 DBC01DR2 26 RW 133 66 A6 E6 DBC01CR0 27 134 I2C1_DR 67 RW 197 A7 E7 DCC02DR0...

Page 112: ...N 20 RW 222 60 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 61 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 62 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 63 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 64 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN 25 RW 224 65 RTC_M A5 RW 276 E5 DBC01OU 26 RW 226 66 RTC_S A6 RW 277 E6 DBC01CR1 27 RW 228 67 RTC_CR...

Page 113: ... 207 DBC00DR0 20 131 60 DEC0_DH A0 RC 169 INT_MSK0 E0 RW 208 DBC00DR1 21 W 132 AMUX_CFG 61 RW 146 DEC0_DL A1 RC 170 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 62 DEC1_DH A2 RC 169 INT_VC E2 RC 210 DBC00CR0 23 134 63 DEC1_DL A3 RC 170 RES_WDT E3 W 211 DBC01DR0 24 131 64 A4 E4 DBC01DR1 25 W 132 65 A5 E5 DBC01DR2 26 RW 133 66 A6 DEC_CR0 E6 RW 212 DBC01CR0 27 134 67 A7 DEC_CR1 E7 RW 213 DCC02DR0 28 131 68 ...

Page 114: ...4 DE RW 294 1F 5F 9F OSC_CR3 DF RW 295 DBC00FN 20 RW 222 60 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 61 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 62 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 63 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 64 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN 25 RW 224 65 RTC_M A5 RW 276 ADC0_TR E5 RW 301 DBC01OU ...

Page 115: ...DD RW 204 1E 5E 9E INT_MSK3 DE RW 206 1F 5F 9F INT_MSK2 DF RW 207 DBC00DR0 20 131 AMX_IN 60 RW 145 DEC0_DH A0 RC 169 INT_MSK0 E0 RW 208 DBC00DR1 21 W 132 AMUX_CFG 61 RW 146 DEC0_DL A1 RC 170 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 CLK_CR3 62 RW 147 DEC1_DH A2 RC 169 INT_VC E2 RC 210 DBC00CR0 23 134 ARF_CR 63 RW 148 DEC1_DL A3 RC 170 RES_WDT E3 W 211 DBC01DR0 24 131 CMP_CR0 64 149 A4 I2C1_SCR E4 195 ...

Page 116: ...SC_CR3 DF RW 295 DBC00FN 20 RW 222 CLK_CR0 60 RW 236 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 CLK_CR1 61 RW 237 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 ABF_CR0 62 RW 238 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 AMD_CR0 63 RW 239 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 CMP_GO_EN 64 RW 240 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN ...

Page 117: ...BC00DR0 20 131 AMX_IN 60 RW 145 DEC0_DH A0 RC 169 INT_MSK0 E0 RW 208 DBC00DR1 21 W 132 AMUX_CFG 61 RW 146 DEC0_DL A1 RC 170 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 CLK_CR3 62 RW 147 DEC1_DH A2 RC 169 INT_VC E2 RC 210 DBC00CR0 23 134 ARF_CR 63 RW 148 DEC1_DL A3 RC 170 RES_WDT E3 W 211 DBC01DR0 24 131 CMP_CR0 64 149 DEC2_DH A4 RC 169 E4 DBC01DR1 25 W 132 ASY_CR 65 150 DEC2_DL A5 RC 170 E5 DBC01DR2 26 ...

Page 118: ...C_CR3 DF RW 295 DBC00FN 20 RW 222 CLK_CR0 60 RW 236 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 CLK_CR1 61 RW 237 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 ABF_CR0 62 RW 238 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 AMD_CR0 63 RW 239 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 CMP_GO_EN 64 RW 240 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN 2...

Page 119: ...5E ASC23CR2 9E RW 163 INT_MSK3 DE RW 206 1F 5F ASC23CR3 9F RW 164 INT_MSK2 DF RW 207 DBC00DR0 20 131 AMX_IN 60 RW 145 DEC0_DH A0 RC 169 INT_MSK0 E0 RW 208 DBC00DR1 21 W 132 AMUX_CFG 61 RW 146 DEC0_DL A1 RC 170 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 CLK_CR3 62 RW 147 DEC1_DH A2 RC 169 INT_VC E2 RC 210 DBC00CR0 23 134 ARF_CR 63 RW 148 DEC1_DL A3 RC 170 RES_WDT E3 W 211 DBC01DR0 24 131 CMP_CR0 64 149 ...

Page 120: ... RW 295 DBC00FN 20 RW 222 CLK_CR0 60 RW 236 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 CLK_CR1 61 RW 237 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 ABF_CR0 62 RW 238 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 AMD_CR0 63 RW 239 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 CMP_GO_EN 64 RW 240 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN 25 RW 224...

Page 121: ... 5F ASC23CR3 9F RW 164 INT_MSK2 DF RW 207 DBC00DR0 20 131 AMX_IN 60 RW 145 DEC0_DH A0 RC 169 INT_MSK0 E0 RW 208 DBC00DR1 21 W 132 AMUX_CFG 61 RW 146 DEC0_DL A1 RC 170 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 CLK_CR3 62 RW 147 DEC1_DH A2 RC 169 INT_VC E2 RC 210 DBC00CR0 23 134 ARF_CR 63 RW 148 DEC1_DL A3 RC 170 RES_WDT E3 W 211 DBC01DR0 24 131 CMP_CR0 64 149 DEC2_DH A4 RC 169 I2C1_SCR E4 195 DBC01DR1 ...

Page 122: ...0 60 RW 236 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 CLK_CR1 61 RW 237 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 ABF_CR0 62 RW 238 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 AMD_CR0 63 RW 239 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 CMP_GO_EN 64 RW 240 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN 25 RW 224 CMP_GO_EN1 65 RW 241 RTC_M A5 R...

Page 123: ... AMUX_CFG 61 RW 146 DEC0_DL A1 RC 170 INT_MSK1 E1 RW 209 DBC00DR2 22 RW 133 CLK_CR3 62 RW 147 DEC1_DH A2 RC 169 INT_VC E2 RC 210 DBC00CR0 23 134 ARF_CR 63 RW 148 DEC1_DL A3 RC 170 RES_WDT E3 W 211 DBC01DR0 24 131 CMP_CR0 64 149 DEC2_DH A4 RC 169 E4 DBC01DR1 25 W 132 ASY_CR 65 150 DEC2_DL A5 RC 170 E5 DBC01DR2 26 RW 133 CMP_CR1 66 RW 151 DEC3_DH A6 RC 169 DEC_CR0 E6 RW 212 DBC01CR0 27 134 DEC3_DL A...

Page 124: ...20 RW 222 CLK_CR0 60 RW 236 GDI_O_IN_CR A0 RW 271 OSC_CR0 E0 RW 296 DBC00IN 21 RW 224 CLK_CR1 61 RW 237 GDI_E_IN_CR A1 RW 272 OSC_CR1 E1 RW 297 DBC00OU 22 RW 226 ABF_CR0 62 RW 238 GDI_O_OU_CR A2 RW 273 OSC_CR2 E2 RW 298 DBC00CR1 23 RW 228 AMD_CR0 63 RW 239 GDI_E_OU_CR A3 RW 274 VLT_CR E3 RW 299 DBC01FN 24 RW 222 CMP_GO_EN 64 RW 240 RTC_H A4 RW 275 VLT_CMP E4 R 300 DBC01IN 25 RW 224 CMP_GO_EN1 65 R...

Page 125: ...124 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...

Page 126: ...ress from lowest to highest 2 Register table showing the bit organization with reserved bits grayed out 3 Written description of register specifics or links to additional register information 4 Detailed register bit descriptions Note that some registers are directly related to the digital and analog functions therefore these registers might have more than one register table number 2 above This is ...

Page 127: ...s the second x set represents Prefix mn Suffix where m row index n column index Therefore DCC32CR0 written DxCxxCR0 is a digital communication register for a digital PSoC block in row 3 column 2 For digital row registers the x in the digital register s name represents the digital row index For example if the RDIxIS register name encompasses four registers there is one for each digital row index an...

Page 128: ...gister allows for write or read access of the current logical equivalent of the voltage on the pin For Port 5 the upper nibble of this register returns the last data bus value when read and should be masked off prior to using this information Note For devices with less than 5 ports the extra registers can be used as temp registers For additional information refer to the Register Definitions on pag...

Page 129: ...ior to using this information For additional information refer to the Register Definitions on page 76 in the GPIO chapter 7 0 Interrupt Enables 7 0 A bit set in this register will enable the corresponding port pin interrupt 0 Port pin interrupt disabled for the corresponding pin 1 Port pin interrupt enabled for the corresponding pin Individual Register Names and Addresses 0 01h PRT0IE 0 01h PRT1IE...

Page 130: ...the GPIO chapter 7 0 Global Select 7 0 A bit set in this register connects the corresponding port pin to an internal global bus This connection is used to input or output digital signals to or from the digital blocks 0 Global function disabled The pin value is determined by the PRTxDR bit value and port configuration registers 1 Global function enabled Direction depends on mode bits for the pin re...

Page 131: ... mode bits are shown in the sub table below 210 refers to the combination in order of bits in a given bit position however this register only controls the most significant bit MSb of the Drive mode For Port 5 the upper nibble of this register returns the last data bus value when read and should be masked off prior to using this information For additional information refer to the Register Definitio...

Page 132: ... Suffix where m row index n column index Therefore DBC21DR0 is a digital basic register for a digital PSoC block in row 2 column 1 Depending on the digital row characteristics of your PSoC device see the table titled PSoC Device Characteristics on page 311 some addresses may not be available For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 0 ...

Page 133: ...tion For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 0 Data 7 0 Data for selected function Block Function Register Function DCC Only Timer Period No Counter Period No Dead Band Period No PWMDBL Period No CRCPRS Polynomial No SPIM TX Buffer Yes SPIS TX Buffer Yes TXUART TX Buffer Yes RXUART Not applicable Yes DSM Initial Phase Yes Individual ...

Page 134: ...Register Definitions on page 348 in the Digital Blocks chapter If the block is configured as SPIM SPIS or RXUART this register is read only 7 0 Data 7 0 Data for selected function Block Function Register Function DCC Only Timer Capture Compare No Counter Compare No Dead Band Buffer No PMWDBL Compare No CRCPRS Seed Residue No SPIM RX Buffer Yes SPIS RX Buffer Yes TXUART Not applicable Yes RXUART RX...

Page 135: ... 0101b RI 1 0110b RI 2 0111b RI 3 1000b RO 0 1001b RO 1 1010b RO 2 1011b RO 3 1100b ACMP 0 1101b ACMP 1 1110b ACMP 2 1111b ACMP 3 3 NPS Negative phase selection The comparison output will be updated only when block clock is 0 2 TC Pulse Width Primary output 0 Terminal Count pulse width is one half a block clock Supports a period value of 00h 1 Terminal Count pulse width is one full block clock 1 C...

Page 136: ...erved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 348 in the Digital Blocks chap ter 7 4 KILL 3 0 Same meaning as in Timer function 3 NPS Same meaning as in Timer function 1 DR2BufEn 1 Enable DR2 update buffer that is update DR2 only at TC when function is running 0 Enable 0 Counter is not enabled 1 Counter is enabled Individ...

Page 137: ...e 348 in the Digital Blocks chap ter 2 Bit Bang Clock When Bit Bang mode is enabled the output of this register bit is substituted for the PWM reference This register may be toggled by user firmware to generate PHI1 and PH2 output clocks with the pro grammed dead time 1 Bit Bang Mode 0 Dead Band Generator uses the previous block primary output as the input reference 1 Dead Band Generator uses the ...

Page 138: ...s on page 348 in the Digital Blocks chap ter 7 4 KILL 3 0 Same as Timer function 2 Shift Mode Forces CRCPRS forward bus to zero to complete shift function 0 Normal CRC PRS operation 1 Shift register operation 1 Pass Mode If selected the DATA input selection is driven directly to the primary output and the block interrupt output The CLK input selection is driven directly to the auxiliary output 0 N...

Page 139: ... 1111b ACMP 3 When the shot is ongoing the new trigger rising edge of START has no effect It will launch a new shot when START stays high at the end of the shot 3 NPS Negative Phase Select 0 Disables negative phase select No delay for compare output to become low 1 Enable negative phase select Compare output will delay one half cycle to become low Note The PWMDBL function does not support NPS mode...

Page 140: ...ode 1 Enables software trigger mode If SWT is set to 1 writing Enable bit 0 to 1 software will start PPG mode If SWT is cleared to 0 PWMDBL will wait for the rising edge of START to trigger PPG 0 Enable 0 Disables PWMDBL function 1 Enables PWMDBL function The primary digital block output is a comparison output or the auxiliary digital block output is the reversed version They support dead band ...

Page 141: ...hifted out and all associated clocks are generated It is cleared on a read of this CR0 register Optional interrupt 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer DR1 register This is the default interrupt This status ...

Page 142: ...is shifted out and all associated clocks are generated It is cleared on a read of this CR0 register Optional interrupt 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer DR1 register This is the default interrupt This sta...

Page 143: ...n page 348 in the Digital Blocks chapter 7 4 KILL_SEL 3 0 Used to select KILL signal source 0000b Low 0001b High 0010b BC 0011b VC3 0100b RI 0 0101b RI 1 0110b RI 2 0111b RI 3 1000b RO 0 1001b RO 1 1010b RO 2 1011b RO 3 1100b ACMP 0 1101b ACMP 1 1110b ACMP 2 1111b ACMP 3 0 Enable 0 Enables DSM function When enabled the DSM starts working 1 Disables DSM function When disabled DSM output is low and ...

Page 144: ...ay still be in the process of shifting out 1 Indicates that a byte is shifted out and all associated framing bits are generated Optional interrupt Cleared on a read of this CR0 register 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX register and cleared on write o...

Page 145: ... cleared on a read of this CR0 register 5 Framing Error 0 Indicates no framing error has occurred 1 Valid when RX Reg Full is set indicating that a framing error has occurred a logic 0 was sampled at the STOP bit instead of the expected logic 1 It is cleared on a read of this CR0 register 4 RX Active 0 Indicates that no reception is in progress 1 Indicates that a reception is in progress It is set...

Page 146: ...b ACM3 P0 0 01b ACM3 P0 2 10b ACM3 P0 4 11b ACM3 P0 6 5 4 ACI2 1 0 Selects the Analog Column Mux 2 00b ACM2 P0 1 01b ACM2 P0 3 10b ACM2 P0 5 11b ACM2 P0 7 3 2 ACI1 1 0 Selects the Analog Column Mux 1 For 1 column these are even inputs 00b ACM1 P0 0 01b ACM1 P0 2 10b ACM1 P0 4 11b ACM1 P0 6 1 0 ACI0 1 0 Selects the Analog Column Mux 0 For 1 column these are odd inputs 00b ACM0 P0 1 01b ACM0 P0 3 10...

Page 147: ...x bus left net connects to column 0 5 4 INTCAP 1 0 Selects pins for static operation even when the precharge clock is selected with MUXCLKx 2 0 00b Both P0 7 and P0 5 are in normal precharge configuration 01b P0 5 pin selected for static mode only 10b P0 7 pin selected for static mode only 11b Both P0 7 and P0 5 are selected for static mode only 3 1 MUXCLK0 2 0 Selects a precharge clock source for...

Page 148: ...s are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 400 in the Analog Interface chapter 3 0 SYSDIR 3 0 0 Associated ACC column s clock source is determined by setting of CLK_CR0 1 Associated ACC column s clock source is SYSCLK Individual Register Names and ...

Page 149: ...lect the sources for analog ground AGND the high reference RefHi and the low reference RefLo The following table applies to 4 and 2 column PSoC devices AGND RefHi RefLo 000b Vdd 2 Vdd 2 Bandgap Vdd 2 Bandgap 001b P2 4 P2 4 P2 6 P2 4 P2 6 010b Vdd 2 Vdd 2 Vdd 2 Vdd 2 Vdd 2 011b 2 x Bandgap 2 x Bandgap Bandgap 2 x Bandgap Bandgap 100b 2 x Bandgap 2 x Bandgap P2 6 2 x Bandgap P2 6 101b P2 4 P2 4 Band...

Page 150: ...sable bits are set refer to the CLDISx bits in the CMP_CR1 register If the comparator latch disable bits are set then this bit is transparent to the comparator bus in the analog array 3 AINT 3 Controls the selection of the analog comparator interrupt for column 3 0 The comparator data bit from the column is the input to the interrupt controller 1 The falling edge of PHI2 for the column is the inpu...

Page 151: ...adjusts the SAR comparator based on the type of block addressed In a DAC configuration with more than one analog block more than 6 bits this bit should be set to 0 when processing the most significant block It should be set to 1 when processing the least significant block because the least significant block is an inverting input to the most significant block 2 1 SARCOL 1 0 The selected column corr...

Page 152: ...tor output latch column 2 0 Comparator bus synchronization is enabled 1 Comparator bus synchronization is disabled 5 CLDIS 1 Controls the comparator output latch column 1 0 Comparator bus synchronization is enabled 1 Comparator bus synchronization is disabled 4 CLDIS 0 Controls the comparator output latch column 0 0 Comparator bus synchronization is enabled 1 Comparator bus synchronization is disa...

Page 153: ... 001 52594 Rev G 0 66h 13 2 24 CMP_CR1 continued 0 CLK1X 0 Controls the digital comparator bus 0 synchronization clock 0 Comparator bit is synchronized by rising edge of PHI2 1 Comparator bit is synchronized directly by selected column clock This clock is not divided by 4 ...

Page 154: ...C28x23 and CY8C28x52 devices For additional information see Regis ter Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 7 0 Data High 7 0 The high byte of ADC data Only the two least significant bits are valid when in right justified mode The ADC can be treated as an 8 bit ADC if you only read this byte of ADC data in left justified mode Individual Register Names and Addresses 0 6Ah...

Page 155: ...28x52 devices For additional information see Regis ter Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 7 0 Data Low 7 0 The low byte of ADC data It contains the least significant 8 bits of the 10 bit sample in right justified data format In left justified data format only the bits 1 0 are valid to hold the least significant 2 bits of the 10 bit sample Individual Register Names and...

Page 156: ... the performance in multiple SRAM page PSoC devices For additional information refer to the Register Definitions on page 60 in the RAM Paging chapter 7 0 Data 7 0 General purpose register space Individual Register Names and Addresses x 6Ch TMP_DR0 x 6Ch TMP_DR1 x 6Dh TMP_DR2 x 6Eh TMP_DR3 x 6Fh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7 0 Bit Name Description ...

Page 157: ... refer to the Register Definitions on page 426 in the Continuous Time Block chapter 5 AGND_PD Used to power down AGND buffer in CT block 0 AGND buffer in CT block enabled 1 AGND buffer in CT block disabled 4 RTopMux1 0 RTop to Vdd or opamp s output depending on ACCxxCR0 bit 2 1 RTop to RefHi 3 LPCMPEN 0 Low power comparator is disabled 1 Low power comparator is enabled 2 CMOUT 0 No connection to c...

Page 158: ...The EXGAIN bit only affects the RTapMux values 0000b and 0001b RTap EXGAIN Rf Ri Loss Gain 0000b 1 47 1 0 0208 48 000 0001b 1 46 2 0 0417 24 000 0000b 0 45 3 0 0625 16 000 0001b 0 42 6 0 1250 8 000 0010b 0 39 9 0 1875 5 333 0011b 0 36 12 0 2500 4 000 0100b 0 33 15 0 3125 3 200 0101b 0 30 18 0 3750 2 667 0110b 0 27 21 0 4375 2 286 0111b 0 24 24 0 5000 2 000 1000b 0 21 27 0 5625 1 778 1001b 0 18 30 ...

Page 159: ...ister is set In that case the bottom of the resistor string is connected across columns Note that available mux inputs vary by individual PSoC block In the following table only columns ACC00 and ACC01 are used by the 2 column analog PSoC blocks and all columns are used by the 4 column analog PSoC blocks ACC00 ACC01 ACC02 ACC03 00b ACC01 ACC00 ACC03 ACC02 01b AGND AGND AGND AGND 10b Vss Vss Vss Vss...

Page 160: ...oC blocks and all columns are used by the 4 column analog PSoC blocks ACC00 ACC01 ACC02 ACC03 000b ACC01 ACC00 ACC03 ACC02 001b AGND AGND AGND AGND 010b RefLo RefLo RefLo RefLo 011b RefHi RefHi RefHi RefHi 100b FB FB FB FB 101b ASC10 ASD11 ASC12 ASD13 110b ASD11 ASC10 ASD13 ASC12 111b Port Inputs Port Inputs Port Inputs Port Inputs Feedback point from tap of the feedback resistor as defined by cor...

Page 161: ...rator Mode 1 Opamp Mode 4 TMUXEN Test Mux 0 Disabled 1 Enabled 3 2 TestMux 1 0 Select block bypass mode Note that available mux inputs vary by individual PSoC block and TMUXEN must be set In the following table column ACC01 is used by the one column PSoC blocks columns ACC00 and ACC01 are used by the 2 column PSoC blocks and all columns are used by the 4 column PSoC blocks ACC00 ACC01 ACC02 ACC03 ...

Page 162: ... the comparator within the switched cap blocks as well as the clock phase of the switches 0 Switch phasing is Internal PHI1 External PHI1 Comparator Capture Point Event is trig gered by Falling PHI2 and Comparator Output Point Event is triggered by Rising PHI1 1 Switch phasing is Internal PHI1 External PHI2 Comparator Capture Point Event is trig gered by Falling PHI1 and Comparator Output Point Ev...

Page 163: ...ary by individual PSoC block For 4 Column Analog PSoC Blocks ASC10 ASC21 ASC12 ASC23 A Inputs C Inputs A Inputs C Inputs A Inputs C Inputs A Inputs C Inputs 000b ACC00 ACC00 ASD11 ASD11 ACC02 ACC02 ASD13 ASD13 001b ASD11 ACC00 ASD20 ASD11 ASD13 ACC02 ASD22 ASD13 010b RefHi ACC00 RefHi ASD11 RefHi ACC02 RefHi ASD13 011b ASD20 ACC00 Vtemp ASD11 ASD22 ACC02 ABUS3 ASD13 100b ACC01 ASD20 ASC10 ASD11 AC...

Page 164: ...ter on page 161 bit 6 also affects this bit Sample Hold mode is allowed only if ClockPhase 0 0 Disable output to analog column bus 1 Enable output to analog column bus 6 CompBus Enable output to the comparator bus 0 Disable output to comparator bus 1 Enable output to comparator bus 5 AutoZero Bit for controlling gated switches 0 Shorting switch is not active Input cap branches shorted to opamp inp...

Page 165: ...et low the input is set to RefLo 5 FSW1 Bit for controlling the FSW1 switch 0 Switch is disabled 1 If the FSW1 bit is set to 1 the state of the switch is determined by the AutoZero bit If the AutoZero bit is 0 the switch is enabled at all times If the AutoZero bit is 1 the switch is enabled only when the Internal PHI2 is high 4 FSW0 Bit for controlling the FSW0 switch 0 Switch is disabled 1 Switch...

Page 166: ... the comparator within the switched cap blocks as well as the clock phase of the switches 0 Switch phasing is Internal PHI1 External PHI1 Comparator Capture Point Event is trig gered by Falling PHI2 and Comparator Output Point Event is triggered by Rising PHI1 1 Switch phasing is Internal PHI1 External PHI2 Comparator Capture Point Event is trig gered by Falling PHI1 and Comparator Output Point Ev...

Page 167: ...witched Capacitor Block chapter 7 5 AMux 2 0 Encoding for selecting A and C inputs for C Type blocks and A inputs for D Type blocks Note that available mux inputs vary by individual PSoC block ASD20 ASD11 ASD22 ASD13 000b ASC10 ACC01 ASC12 ACC03 001b P2 1 ASC12 ASC21 P2 2 010b ASC21 ASC10 ASC23 ASC12 011b ABUS0 ASC21 ABUS2 ASC23 100b RefHi RefHi RefHi RefHi 101b ASD11 ACC00 ASD13 ACC02 110b Reserv...

Page 168: ...egister bit 6 also affect this bit Sample Hold mode is allowed only if ClockPhase 0 0 Disable output to analog column bus 1 Enable output to analog column bus 6 CompBus Enable output to the comparator bus 0 Disable output to comparator bus 1 Enable output to comparator bus 5 AutoZero Bit for controlling the AutoZero switch 0 Shorting switch is not active Input cap branches shorted to opamp input 1...

Page 169: ...ng gated switches 0 Switch is disabled 1 If the FSW1 bit is set to 1 the state of the switch is determined by the AutoZero bit If the AutoZero bit is 0 the switch is enabled at all times If the AutoZero bit is 1 the switch is enabled only when the Internal PHI2 is high 4 FSW0 Bits for controlling gated switches 0 Switch is disabled 1 Switch is enabled when PHI1 is high 3 BSW Enable switching in br...

Page 170: ...of the decimator is reset but the output data registers DECx_DH and DECx_DL are not For additional information refer to the Register Definitions on page 488 in the Decimator chapter 7 0 Data High Byte 7 0 Read Returns the high byte of the decimator Write Clears the 16 bit accumulator values for one of the decimators Either the DECx_DH or DECx_DL register may be written to clear the accumulators th...

Page 171: ... DECx_DH and DECx_DL are not For additional information refer to the Register Definitions on page 488 in the Decimator chapter 7 0 Data Low Byte 7 0 Read Returns the low byte of the decimator Write Clears the 16 bit accumulator values for one of the decimators Either the DECx_DH or DECx_DL register may be written to clear the accumulators that is it is not necessary to write both Individual Regist...

Page 172: ...signed 8 bit multiplier in the PSoC MAC This register is for 2 MAC block PSoC devices only For additional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 X multiplicand for MAC 8 bit multiplier Individual Register Names and Addresses 0 A8h MUL1_X 0 A8h MUL0_X 0 E8h 7 6 5 4 3 2 1 0 Access POR W XX Bit Name Data 7 0 Bit Name Description ...

Page 173: ...signed 8 bit multiplier in the PSoC MAC This register is for 2 MAC block PSoC devices only For additional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 Y multiplicand for MAC 8 bit multiplier Individual Register Names and Addresses 0 A9h MUL1_Y 0 A9h MUL0_Y 0 E9h 7 6 5 4 3 2 1 0 Access POR W XX Bit Name Data 7 0 Bit Name Description ...

Page 174: ...byte of the 16 bit product This register is for 2 MAC block PSoC devices only For additional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 High byte of MAC multiplier 16 bit product Individual Register Names and Addresses 0 AAh MUL1_DH 0 AAh MUL0_DH 0 EAh 7 6 5 4 3 2 1 0 Access POR R XX Bit Name Data 7 0 Bit Name Description ...

Page 175: ... byte of the 16 bit product This register is for 2 MAC block PSoC devices only For additional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 Low byte of MAC multiplier 16 bit product Individual Register Names and Addresses 0 ABh MUL1_DL 0 ABh MUL0_DL 0 EBh 7 6 5 4 3 2 1 0 Access POR R XX Bit Name Data 7 0 Bit Name Description ...

Page 176: ...ks For additional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the second byte of the 32 bit accumulated value The second byte is next to the least significant byte for the accumulated value Write X multiplicand for the MAC 16 bit multiply and 32 bit accumulator Individual Register Names and Addresses 0 ACh MAC1_X ACC1_DR1 0...

Page 177: ... blocks For additional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the first byte of the 32 bit accumulated value The first byte is the least significant byte for the accumulated value Write Y multiplicand for the MAC 16 bit multiply and 32 bit accumulate Individual Register Names and Addresses 0 ADh MAC1_Y ACC1_DR0 0 ADh M...

Page 178: ...tional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the fourth byte of the 32 bit accumulated value The fourth byte is the most signif icant byte MSB for the accumulated value Write Writing any value to this address will clear all four bytes of the Accumulator Individual Register Names and Addresses 0 AEh MAC1_CL0 ACC1_DR3 0...

Page 179: ...dditional information refer to the Register Definitions on page 478 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the third byte of the 32 bit accumulated value The third byte is the next to most sig nificant byte for the accumulated value Write Writing any value to this address will clear all four bytes of the Accumulator Individual Register Names and Addresses 0 AFh MAC1_CL1 ACC1_...

Page 180: ...ddresses may not be available For additional information refer to the Register Definitions on page 329 in the Row Digital Interconnect chapter 7 6 RI3 1 0 Select source for row input 3 00b GIE 3 01b GIE 7 10b GIO 3 11b GIO 7 5 4 RI2 1 0 Select source for row input 2 00b GIE 2 01b GIE 6 10b GIO 2 11b GIO 6 3 2 RI1 1 0 Select source for row input 1 00b GIE 1 01b GIE 5 10b GIO 1 11b GIO 5 1 0 RI0 1 0...

Page 181: ... be written with a value of 0 For additional information refer to the Register Definitions on page 329 in the Row Dig ital Interconnect chapter 3 RI3SYN 0 Row input 3 is synchronized to the SYSCLK system clock 1 Row input 3 is passed without synchronization 2 RI2SYN 0 Row input 2 is synchronized to the SYSCLK system clock 1 Row input 2 is passed without synchronization 1 RI1SYN 0 Row input 1 is sy...

Page 182: ...ons on page 329 in the Row Dig ital Interconnect chapter 5 4 BCSEL 1 0 When the BCSEL value is equal to the row number the tri state buffer that drives the row broadcast net from the input select mux is disabled so that one of the row s blocks may drive the local row broadcast net 00b Row 0 drives row broadcast net 01b Row 1 drives row broadcast net 10b Row 2 drives row broadcast net Reserved for ...

Page 183: ...istics on page 311 some addresses may not be available For additional information refer to the Register Definitions on page 329 in the Row Digital Interconnect chapter 7 4 LUT1 3 0 Select logic function for LUT1 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAN...

Page 184: ...xLT0 x B3h 13 2 53 RDIxLT0 continued 3 0 LUT0 3 0 Select logic function for LUT0 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE ...

Page 185: ...istics on page 311 some addresses may not be available For additional information refer to the Register Definitions on page 329 in the Row Digital Interconnect chapter 7 4 LUT3 3 0 Select logic function for LUT3 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAN...

Page 186: ...xLT1 x B4h 13 2 54 RDIxLT1 continued 3 0 LUT2 3 0 Select logic function for LUT2 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE ...

Page 187: ... GOO1EN 0 Disable Row s LUT1 output to global output 1 Enable Row s LUT1 output to GOO 1 5 GOE5EN 0 Disable Row s LUT1 output to global output 1 Enable Row s LUT1 output to GOE 5 4 GOE1EN 0 Disable Row s LUT1 output to global output 1 Enable Row s LUT1 output to GOE 1 3 GOO4EN 0 Disable Row s LUT0 output to global output 1 Enable Row s LUT0 output to GOO 4 2 GOO0EN 0 Disable Row s LUT0 output to g...

Page 188: ... GOO3EN 0 Disable Row s LUT3 output to global output 1 Enable Row s LUT3 output to GOO 3 5 GOE7EN 0 Disable Row s LUT3 output to global output 1 Enable Row s LUT3 output to GOE 7 4 GOE3EN 0 Disable Row s LUT3 output to global output 1 Enable Row s LUT3 output to GOE 3 3 GOO6EN 0 Disable Row s LUT2 output to global output 1 Enable Row s LUT2 output to GOO 6 2 GOO2EN 0 Disable Row s LUT2 output to g...

Page 189: ...initions on page 329 in the Row Digital Interconnect chapter 7 4 AVG_SEL 3 0 Selects digital block output as average control signal 0000b DBC00 0001b DBC01 0010b DCC02 0011b DCC03 0100b DBC10 0101b DBC11 0110b DCC12 0111b DCC13 1000b DBC20 1001b DBC21 1010b DCC22 1011b DCC23 1100b low 1101b low 1110b low 1111b low 3 0 AVG_EN 3 0 Enables average function on corresponding RO channel AVG_EN 0 0 Disab...

Page 190: ... value of 0 For additional information refer to the Register Definitions on page 60 in the RAM Paging chapter 2 0 Page Bits 2 0 These bits determine which SRAM Page is used for generic SRAM access See the RAM Paging chapter on page 57 for more information 000b SRAM Page 0 001b SRAM Page 1 010b SRAM Page 2 011b SRAM Page 3 100b SRAM Page 4 101b SRAM Page 5 110b SRAM Page 6 111b SRAM Page 7 Note A v...

Page 191: ...a value of 0 For additional information refer to the Register Definitions on page 60 in the RAM Paging chapter 2 0 Page Bits 2 0 These bits determine which SRAM Page is used to hold the stack See the RAM Paging chapter on page 57 for more information 000b SRAM Page 0 001b SRAM Page 1 010b SRAM Page 2 011b SRAM Page 3 100b SRAM Page 4 101b SRAM Page 5 110b SRAM Page 6 111b SRAM Page 7 Note A value ...

Page 192: ...For additional information refer to the Register Definitions on page 60 in the RAM Paging chapter 2 0 Page Bits 2 0 These bits determine which SRAM Page an indexed memory access operates on See the Register Definitions on page 60 for more information on when this register is active 000b SRAM Page 0 001b SRAM Page 1 010b SRAM Page 2 011b SRAM Page 3 100b SRAM Page 4 101b SRAM Page 5 110b SRAM Page ...

Page 193: ...ould always be written with a value of 0 For additional information refer to the Register Definitions on page 60 in the RAM Paging chapter 2 0 Page Bits 2 0 These bits determine which SRAM Page a MVI Read instruction operates on 000b SRAM Page 0 001b SRAM Page 1 010b SRAM Page 2 011b SRAM Page 3 100b SRAM Page 4 101b SRAM Page 5 110b SRAM Page 6 111b SRAM Page 7 Note A value beyond the available S...

Page 194: ...hould always be written with a value of 0 For additional information refer to the Register Definitions on page 60 in the RAM Paging chapter 2 0 Page Bits 2 0 These bits determine which SRAM Page a MVI Write instruction operates on 000b SRAM Page 0 001b SRAM Page 1 010b SRAM Page 2 011b SRAM Page 3 100b SRAM Page 4 101b SRAM Page 5 110b SRAM Page 6 111b SRAM Page 7 Note A value beyond the available...

Page 195: ...C chapter for a discussion of the side effects of choosing the P1 0 and P1 1 pair of pins 5 Bus Error IE Bus Error Interrupt Enable 0 Disabled 1 Enabled An interrupt is generated on the detection of a Bus Error 4 Stop IE Stop Interrupt Enable 0 Disabled 1 Enabled An interrupt is generated on the detection of a Stop Condition 3 2 Clock Rate 1 0 00b 100K Standard Mode 01b 400K Fast Mode 10b 50K Stan...

Page 196: ...p Status 0 This status bit must be cleared by firmware with write of 0 to the bit position It is never cleared by the hardware 1 A Stop condition was detected 4 ACK Acknowledge Out This bit is automatically cleared by hardware on a Byte Complete event 0 NAK the last received byte 1 ACK the last received byte 3 Address 0 This status bit must be cleared by firmware with write of 0 to the bit positio...

Page 197: ...it Receive Mode 0 No completed transmit receive since last cleared by firmware Any Start detect or a write to the Start or Restart generate bits when operating in Master mode will also clear the bit Transmit Mode 1 Eight bits of data have been transmitted and an ACK or NAK has been received Receive Mode 1 Eight bits of data have been received ...

Page 198: ...e CY8C28x03 CY8C28x23 CY8C28x43 and CY8C28x45 PSoC devices only This register is read only for received data and write only for transmitted data For additional information refer to the Register Definitions on page 497 in the I2 C chapter 7 0 Data 7 0 Read received data or write data to transmit Individual Register Names and Addresses 0 D8h I2C1_DR 0 67h I2C0_DR 0 D8h 7 6 5 4 3 2 1 0 Access POR RW ...

Page 199: ... 3 Bus Busy This bit is set to the following 0 When a Stop condition is detected from any bus master 1 When a Start condition is detected from any bus master 2 Master Mode This bit is set cleared by hardware when the device is operating as a master 0 Stop condition detected generated by this device 1 Start condition detected generated by this device 1 Restart Gen This bit is cleared by hardware wh...

Page 200: ... effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for Variable Clock 3 6 Sleep Read 0 No posted interrupt for sleep timer Read 1 Posted interrupt present for sleep timer Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for sleep timer 5 GPIO Read 0 No poste...

Page 201: ...ed interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for analog columns 1 Analog 0 Read 0 No posted interrupt for analog columns Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1...

Page 202: ...ommunications Block type B row 1 position 3 Read 0 No posted interrupt Read 1 Posted interrupt present Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt 6 DCC12 Digital Communications Block type B row 1 position 2 Read 0 No posted interrupt Read 1 Posted interrupt present Write 0 AND ENS...

Page 203: ...WINT 1 Post an interrupt 2 DCC02 Digital Communications Block type B row 0 position 2 Read 0 No posted interrupt Read 1 Posted interrupt present Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt 1 DBC01 Digital Basic Block type B row 0 position 1 Read 0 No posted interrupt Read 1 Posted ...

Page 204: ...ommunications Block type B row 2 position 3 Read 0 No posted interrupt Read 1 Posted interrupt present Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt 2 DCC22 Digital Communications Block type B row 2 position 2 Read 0 No posted interrupt Read 1 Posted interrupt present Write 0 AND ENS...

Page 205: ...ller chapter 5 Analog 5 Read 0 No posted interrupt for analog column 5 Read 1 Posted interrupt present for analog column 5 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for analog column 5 4 Analog 4 Read 0 No posted interrupt for analog column 4 Read 1 Posted interrupt present for a...

Page 206: ...ND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for I2C1 0 I2C0 Read 0 No posted interrupt for I2C0 Read 1 Posted interrupt present for I2C0 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an in...

Page 207: ...should always be written with a value of 0 For additional information refer to the Register Definitions on page 68 in the Interrupt Controller chapter 7 ENSWINT 0 Disable software interrupts 1 Enable software interrupts 5 Analog 5 0 Mask Analog 5 interrupt 1 Unmask Analog 5 interrupt 4 Analog 4 0 Mask Analog 4 interrupt 1 Unmask Analog 4 interrupt 3 RTC 0 Mask RTC interrupt 1 Unmask RTC interrupt ...

Page 208: ...always be written with a value of 0 For additional information refer to the Register Definitions on page 68 in the Interrupt Controller chapter 3 DCC23 0 Mask Digital Communication Block row 2 position 3 interrupt 1 Unmask Digital Communication Block row 2 position 3 interrupt 2 DCC22 0 Mask Digital Communication Block row 2 position 2 interrupt 1 Unmask Digital Communication Block row 2 position ...

Page 209: ...ns on page 68 in the Interrupt Controller chapter 7 VC3 0 Mask VC3 interrupt 1 Unmask VC3 interrupt 6 Sleep 0 Mask sleep interrupt 1 Unmask sleep interrupt 5 GPIO 0 Mask GPIO interrupt 1 Unmask GPIO interrupt 4 Analog 3 0 Mask analog interrupt column 3 1 Unmask analog interrupt 3 Analog 2 0 Mask analog interrupt column 2 1 Unmask analog interrupt 2 Analog 1 0 Mask analog interrupt column 1 1 Unmas...

Page 210: ... 2 interrupt 1 Unmask Digital Communication Block row 1 position 2 interrupt 5 DBC11 0 Mask Digital Basic Block row 1 position 1interrupt 1 Unmask Digital Basic Block row 1 position 1 interrupt 4 DBC10 0 Mask Digital Basic Block row 1 position 0 interrupt 1 Unmask Digital Basic Block row 1 position 0 interrupt 3 DCC03 0 Mask Digital Communication Block row 0 position 3 off 1 Unmask Digital Communi...

Page 211: ...ng interrupts when written For additional information refer to the Register Definitions on page 68 in the Interrupt Controller chapter 7 0 Pending Interrupt 7 0 Read Returns vector for highest priority pending interrupt Write Clears all pending and posted interrupts Individual Register Names and Addresses 0 E2h INT_VC 0 E2h 7 6 5 4 3 2 1 0 Access POR RC 00 Bit Name Pending Interrupt 7 0 Bit Name D...

Page 212: ... both the watchdog timer and the sleep timer For additional information refer to the Register Definitions on page 99 in the Sleep and Watchdog chapter 7 0 WDSL_Clear 7 0 Any write clears the watchdog timer A write of 38h clears both the watchdog and sleep timers Individual Register Names and Addresses 0 E3h RES_WDT 0 E3h 7 6 5 4 3 2 1 0 Access POR W 00 Bit Name WDSL_Clear 7 0 Bit Name Description ...

Page 213: ...11b Digital block 11 1011b Digital block 31 0100b Digital block 00 1100b Digital block 20 0101b Digital block 10 1101b Digital block 30 0110b Digital block 03 1110b Digital block 23 0111b Digital block 13 1111b Digital block 33 2 1 ACE_IGEN 1 0 Incremental Gate Enable Selects on a Type E column basis which Type E comparator outputs will be gated with the Digital block source selected in ICLKS 3 0 ...

Page 214: ...ital block 12 1001b Digital block 32 0010b Digital block 01 1010b Digital block 21 0011b Digital block 11 1011b Digital block 31 0100b Digital block 00 1100b Digital block 20 0101b Digital block 10 1101b Digital block 30 0110b Digital block 03 1110b Digital block 23 0111b Digital block 13 1111b Digital block 33 2 0 DCLKS 3 1 Decimator Latch Select Along with DCLKS0 in DEC_CR0 selects any one of th...

Page 215: ... are referred to the RAM page specified by the stack page pointer STK_PP 10b Direct Address mode instructions are referred to the RAM page specified by the current page pointer CUR_PP Indexed Address mode instructions are referred to the RAM page specified by the index page pointer IDX_PP 11b Direct Address mode instructions are referred to the RAM page specified by the current page pointer CUR_PP...

Page 216: ...iplexer chapter 7 0 IDACx This 8 bit value selects the number of current units that combine to form the DAC current This cur rent then drives the analog mux bus when DAC mode is enabled in the IDAC_CRx register For example a setting of 80h means that the charging current will be 128 current units The current unit size depends on the range setting in the IDAC_CRx register Individual Register Names ...

Page 217: ...xecuted once 1 Boot phase occurred multiple times 4 SLIMO Reduces frequency of the internal main oscillator IMO 0 IMO produces 24 MHz 1 Slow IMO 6 MHz 3 ECO EXW ECO Exists Written 1 The ECO Exists Written bit has been written with a 1 or 0 and is now locked 0 The ECO Exists Written bit has never been written in User mode 2 ECO EX ECO Exists write once see the explanation in Register Definitions on...

Page 218: ...GIES Its use is discouraged as the Flag register is now readable at address x F7h read only 5 WDRS Watchdog Reset Status This bit may not be set by user code however it may be cleared by writing it with a 0 0 No Watchdog Reset has occurred 1 Watchdog Reset has occurred 4 PORS Power On Reset Status This bit may not be set by user code however it may be cleared by writing it with a 0 0 Power On Rese...

Page 219: ...rs are treated as a group These are referred to as DM2 DM1 and DM0 or together as DM 2 0 All Drive mode bits are shown in the sub table below 210 refers to the combination in order of bits in a given bit position however this register only controls the least significant bit LSb of the Drive mode For Port 5 the upper nibble of this register will return the last data bus value when read and should b...

Page 220: ...bits are shown in the sub table below 210 refers to the combination in order of bits in a given bit position however this register only controls the middle bit of the Drive mode For Port 5 the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information For additional information refer to the Register Definitions on page 76 in...

Page 221: ...n for example Bit 2 in PRT0IC0 and bit 2 in PRT0IC1 The two bits from the two registers are treated as a group In the sub table below 0 refers to the combination in order of bits in a given position one bit from PRTxIC1 and one bit from PRTxIC0 For Port 5 the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information For add...

Page 222: ...n for example Bit 2 in PRT0IC0 and bit 2 in PRT0IC1 The two bits from the two registers are treated as a group In the sub table below 1 refers to the combination in order of bits in a given position one bit from PRTxIC1 and one bit from PRTxIC0 For Port 5 the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information For add...

Page 223: ...ice some addresses may not be available For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 Data Invert 0 Data input is non inverted 1 Data input is inverted 6 BCEN Enable Primary Function Output to drive the broadcast net 0 Disable 1 Enable 5 End Single 0 Block is not the end of a chained function or the function is not chainable 1 Block is the...

Page 224: ...de 1 signifies the Interrupt Type 0 Interrupt on TX Reg Empty 1 Interrupt on TX Complete SPI Mode 0 signifies the Type 0 Master 1 Slave Mode 1 signifies the Interrupt Type 0 Interrupt on TX Reg Empty 1 Interrupt on SPI Complete DSM DSM Kill Mode 0 KILL Async Mode 1 KILL Disable Mode Mode 0 DSM Multiplication Mode 0 Density Multiplier for Single Reference 1 Density Multiplier for Bipolar Reference ...

Page 225: ... index Therefore DCC12IN is a digital communication register for a digital PSoC block in row 1 column 2 Depending on the digital row characteristics of your PSoC device some addresses may not be available For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 4 Data Input 3 0 0000b Low 0 0001b High 1 0010b Row broadcast net 0011b Chain function to ...

Page 226: ...0 Clock Input 3 0 0000b Clock disabled low 0001b VC3 0010b Row broadcast net 0011b Previous block primary output low for DBC00 0100b SYSCLKX2 0101b VC1 0110b VC2 0111b CLK32K 1000b Row output 0 1001b Row output 1 1010b Row output 2 1011b Row output 3 1100b Row input 0 1101b Row input 1 1110b Row input 2 1111b Row input 3 ...

Page 227: ...f your PSoC device some addresses may not be available For addi tional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 6 AUXCLK 00b No sync 16 to 1 clock mux output 01b Synchronize Output of 16 to 1 clock mux to SYSCLK 10b Synchronize Output of 16 to 1 clock mux to SYSCLKX2 11b SYSCLK Directly connect SYSCLK to block clock input 5 AUXEN Auxiliary I O Enabl...

Page 228: ...X IO Select 1 0 SPI Slave Source for SS_ Input if AUXEN 1 cont 00b Force SS_ Active 01b Reserved 10b Reserved 11b Reserved 2 OUTEN Enable Primary Function Output Driver 0 Disabled 1 Enabled 1 0 Output Select 1 0 Row Output Select for Primary Function Output 00b Row Output 0 01b Row Output 1 10b Row Output 2 11b Row Output 3 ...

Page 229: ...loaded on every block clock The multi shot counter is reloaded on the first rising edge of the block clock after the kill signal is deasserted This is also when the down counter starts counting again When the kill signal is asserted both digital block outputs are held low 11b Kill Disable mode The block is immediately disabled when the kill signal is asserted Both block outputs are held low The bl...

Page 230: ...efer to the Register Definitions on page 348 in the Digital Blocks chapter 7 4 Multi Shot Has same meaning as in Timer 3 KILL_INV Same as Timer 2 1 KILL_MD 1 0 Same as Timer 0 KILL_INT Same as Timer Individual Register Names and Addresses 1 23h DBC00CR1 1 23h DBC01CR1 1 27h DCC02CR1 1 2Bh DCC03CR1 1 2Fh DBC10CR1 1 33h DBC11CR1 1 37h DCC12CR1 1 3Bh DCC13CR1 1 3Fh DBC20CR1 1 43h DBC21CR1 1 47h DCC22...

Page 231: ...fer to the Register Definitions on page 348 in the Digital Blocks chapter 7 4 Multi Shot Has same meaning as in Timer 3 KILL_INV Same as Timer 2 1 KILL_MD 1 0 Same as Timer 0 KILL_INT Same as Timer Individual Register Names and Addresses 1 23h DBC00CR1 1 23h DBC01CR1 1 27h DCC02CR1 1 2Bh DCC03CR1 1 2Fh DBC10CR1 1 33h DBC11CR1 1 37h DCC12CR1 1 3Bh DCC13CR1 1 3Fh DBC20CR1 1 43h DBC21CR1 1 47h DCC22C...

Page 232: ...e the function is in PPG mode and the iteration time by one trigger is specified by these 4 multi shot bits 3 STARTINV 0 Normal Start signal 1 Invert Start signal 2 0 DBW 2 0 Dead Band Width 000b No Dead Band 001b 1 BLKCLK Dead Band 010b 2 BLKCLK Dead Band 011b 4 BLKCLK Dead Band 100b 8 BLKCLK Dead Band 101b 16 BLKCLK Dead Band 110b 32 BLKCLK Dead Band 111b 64 BLKCLK Dead Band Individual Register ...

Page 233: ... described in the bit description section Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 0 KILL_INT 0 Kill signal is not interrupt source 1 Kill signal is interrupt source and has highest priority Individual Register Names and Addresses 1 23h DBC00CR1 1 23h DBC01CR1 1 27h DCC02CR1 1 2Bh...

Page 234: ...th a value of 0 For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 Chain 0 Block is not part of an SPI chain 1 Block is in an SPI chain 6 LSB 0 Block is MSB in SPI chain 1 Block is LSB in SPI chain Note Bit 7 must be set to use this bit 4 0 SPI Length Specifies the SPI length in chain mode Individual Register Names and Addresses 1 23h DBC00CR1 ...

Page 235: ...th a value of 0 For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 7 Chain 0 Block is not part of an SPI chain 1 Block is in an SPI chain 6 LSB 0 Block is MSB in SPI chain 1 Block is LSB in SPI chain Note Bit 7 must be set to use this bit 4 0 SPI Length Specifies the SPI length in chain mode Individual Register Names and Addresses 1 23h DBC00CR1 ...

Page 236: ...tion section Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 348 in the Digital Blocks chapter 3 KILL_INV 0 Do not invert Kill signal 1 Invert Kill signal 0 KILL_INT 0 Select CO as interrupt 1 Select KILL as interrupt Individual Register Names and Addresses 1 23h DBC00CR1 1 23h DBC01CR1 1 27h DCC02CR1 1 2Bh DCC03CR1 1 2F...

Page 237: ...umn 3 00b Variable Clock 1 VC1 01b Variable Clock 2 VC2 10b Analog Clock 0 ACLK0 11b Analog Clock 1 ACLK1 5 4 AColumn2 1 0 Clock selection for column 2 00b Variable Clock 1 VC1 01b Variable Clock 2 VC2 10b Analog Clock 0 ACLK0 11b Analog Clock 1 ACLK1 3 2 AColumn1 1 0 Clock selection for column 1 00b Variable Clock 1 VC1 01b Variable Clock 2 VC2 10b Analog Clock 0 ACLK0 11b Analog Clock 1 ACLK1 1 ...

Page 238: ...ing source for Analog Clock 1 000b Digital Basic Block 00 or 20 001b Digital Basic Block 01 or 21 010b Digital Communication Block 02 or 22 011b Digital Communication Block 03 or 23 100b Digital Basic Block 10 101b Digital Basic Block 11 110b Digital Communication Block 12 111b Digital Communication Block 13 Note Selection determined by setting of ACLK1R 2 0 ACLK0 2 0 Select the clocking source fo...

Page 239: ... 1 Pin P0 5 0 Disable analog output buffer 1 Enable analog output buffer 4 ABUF2EN Enables the analog output buffer for Analog Column 2 Pin P0 4 0 Disable analog output buffer 1 Enable analog output buffer 3 ABUF0EN Enables the analog output buffer for Analog Column 0 Pin P0 3 0 Disable analog output buffer 1 Enable analog output buffer 2 ABUF3EN Enables the analog output buffer for Analog Column ...

Page 240: ...n for column 2 000b Zero off 001b Global Output Bus even bus bit 1 GOE 1 010b Global Output Bus even bus bit 0 GOE 0 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comparator 3 2 0 AMOD0 2 0 Analog modulation control signal selection for column 0 000b Zero off 001b Global Output Bus even bus bit 1 GOE 1 01...

Page 241: ...olumn 1 1 Column 1 drives GOO1 5 4 SEL1 1 0 Selects the column 1 signal to output 00b Comparator bus output 01b PHI1 column clock 10b PHI2 column clock 11b Selected column clock direct 1X 3 GOO4 Drives the selected column 0 signal to GOO4 0 No connection to GOO4 from column 0 1 Column 0 drives GOO4 2 GOO0 Drives the selected column 0 signal to GOO0 0 No connection to GOO0 from column 0 1 Column 0 ...

Page 242: ...OO3 0 No connection to GOO3 from column 3 1 Column 3 drives GOO3 5 4 SEL3 1 0 Selects the column 3 signal to output 00b Comparator bus output 01b PHI1 column clock 10b PHI2 column clock 11b PHI1 unsynchronized comparator bus 3 GOO6 Drives the selected column 2 signal to GOO6 0 No connection to GOO6 from column 2 1 Column 2 drives GOO6 2 GOO2 Drives the selected column 2 signal to GOO2 0 No connect...

Page 243: ...n for column 3 000b Zero off 001b Global Output Bus even bus bit 1 GOE 1 010b Global Output Bus even bus bit 0 GOE 0 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comparator 3 2 0 AMOD1 2 0 Analog modulation control signal selection for column 1 000b Zero off 001b Global Output Bus even bus bit 1 GOE 1 01...

Page 244: ...b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE 3 0 LUT0 3 0 Select 1 of 16 logic functions for output of comparator bus 0 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B ...

Page 245: ...tor bus 3 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE 3 0 LUT2 3 0 Select 1 of 16 logic functions for output of comparator bus 2 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b ...

Page 246: ...at reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional informa tion see Register Definitions on page 400 in the Analog Interface chapter 3 ACLK1R Analog Clock 1 Selection Range 0 Select Digital PSoC Block from row 0 and 1 00 13 1 Select Digital PSoC Block from row 2 and 3 20 33 0 ACLK0R An...

Page 247: ...mong P0 6 4 2 0 1 Select analog column 3 input to analog column 2 input mux output Selects among P0 7 5 3 1 4 ACol0Mux 0 Select analog column 0 input to analog column 0 input mux output Selects among P0 7 5 3 1 1 Select analog column 0 input to analog column 1 input mux output Selects among P0 6 4 2 0 3 1 MUXCLK1 2 0 Selects a precharge clock source for analog mux bus right AMuxBus1 connections It...

Page 248: ...AR ADC Controller chapter 7 4 TS_INCMP_SEL Indicates the external source GIE 7 0 or internal source ACC_ACMP 3 0 or ACE_ACMP 1 0 0000b to 0111b Select GIE 0 7 1000b to 1011b Select ACC_ACMP 0 3 1100b to 1101b Select ACE_ACMP 0 1 1110b to 1111b Reserved 3 INCMP_INV 1 Use inverted version of INCMP 2 INCMP_EN 1 Enable INCMP trigger source 1 CMPH_EN 1 Enable high channel trigger source 0 CMPL_EN 1 Ena...

Page 249: ...ns on page 541 in the 10 Bit SAR ADC Controller chapter 6 4 TS_CMPH_SEL 2 0 Selects a digital block s DR0 register to compare against SADC_TSCMPH When the comparison is equal an ADC sample is triggered 000b DBB00 001b DBB01 010b DCB02 011b DCB03 100b DBB10 101b DBB11 110b DCB12 111b DCB13 2 0 TS_CMPL_SEL 2 0 Selects a digital block s DR0 register to compare against SADC_TSCMPL When the comparison ...

Page 250: ...b Global Output Bus even bus bit 1 GOE 1 0010b Global Output Bus even bus bit 0 GOE 0 0011b Row 0 Broadcast Bus 0100b Analog Column Comparator 4 0101b Analog Column Comparator 5 0110b Analog Column Comparator 0 0111b Analog Column Comparator 1 1000b Reserved Zero 1001b Row 1 Broadcast Bus 1010b Row 1 Broadcast Bus 1011b Reserved High 1100b Analog Column Comparator 4 single synchronized 1101b Analo...

Page 251: ...tional information see Register Definitions on page 452 in the Two Column Limited Analog System chapter 3 2 ACI5 1 0 Selects the Analog Column Mux 5 00b ACM5 P0 0 01b ACM5 P0 2 10b ACM5 P0 4 11b ACM5 P0 6 1 0 ACI4 1 0 Selects the Analog Column Mux 4 00b ACM4 P0 1 01b ACM4 P0 3 10b ACM4 P0 5 11b ACM4 P0 7 Individual Register Names and Addresses 1 75h ACE_AMX_IN 1 75h 2L Column 7 6 5 4 3 2 1 0 Acces...

Page 252: ...umn 4 This bit is updated on the rising edge of PHI2 unless the comparator latch disable bits are set refer to the CLDISx bits in the ACE_CMP_CR1 register If the comparator latch disable bits are set then this bit is transparent to the comparator bus in the analog array 1 AINT 5 Controls the selection of the analog comparator interrupt for column 5 0 The comparator data bit from the column is the ...

Page 253: ...grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 452 in the Two Column Limited Analog System chapter 5 CLDIS 5 Controls the comparator output latch column 5 0 Comparator bus synchronization is enabled 1 Comparator bus synchronization is disabled 4 CLDIS 4 Cont...

Page 254: ...Comparator bus output 01b Column clock 10b Comparator output after single sync 11b Column clock gated with the synchronized comparator bus 3 GIO4 Drives the selected column 4 signal to GIO4 0 No connection to GIO4 from column 4 1 Column 4 drives GIO4 2 GIO0 Drives the selected column 4 signal to GIO0 0 No connection to GIO0 from column 4 1 Column 4 drives GIO0 1 0 SEL4 1 0 Selects the column 4 sig...

Page 255: ...LSE 0011b A 1100b A 1111b TRUE 3 0 LUT4 3 0 Select 1 of 16 logic functions for output of comparator bus 4 Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE Individual Register Names and Addresses 1 7Ah ACE_ALT_CR0 1 7Ah 2L Column 7 6 5 4 3 2 1 0 A...

Page 256: ...column 5 input to analog column 5 input mux output P0 6 4 2 0 1 Set analog column 5 input to analog column 4 input mux output P0 7 5 3 1 6 ACE0Mux 0 Set analog column 4 input to analog column 4 input mux output P0 7 5 3 1 1 Set analog column 4 input to analog column 5 input mux output P0 6 4 2 0 Individual Register Names and Addresses 1 7Bh ACE_ABF_CR0 1 7Bh 2L Column 7 6 5 4 3 2 1 0 Access POR RW...

Page 257: ...ut select Note that available mux inputs vary by individual PSoC block ACE00 ACE01 000b ACE01 ACE00 001b VBG VBG 010b Reserved Reserved 011b Muxbus0 Muxbus1 Chip wide analog mux bus 100b FB FB 101b ASE10 ASE11 110b ASE11 ASE10 111b Port Inputs AC4 Port Inputs AC5 Feedback Gain 1 configuration only 2 0 PMux 2 0 Encoding for positive input select Note that available mux inputs vary by individual PSo...

Page 258: ... information see Register Definitions on page 452 in the Two Col umn Limited Analog System chapter 1 FullRange 0 Input range includes Vss but not Vdd 1 Rail to rail input range with approximately 10 A additional cell current 0 PWR 0 Powers off both the CT and SC blocks in the column 1 Enables the column s analog blocks Individual Register Names and Addresses 1 7Eh ACE00CR2 1 7Eh ACE01CR2 1 8Eh 2L ...

Page 259: ...e written with a value of 0 For additional information see Register Definitions on page 452 in the Two Col umn Limited Analog System chapter 7 FVal F Capacitor value selection bit 0 Slower integration in the SC block higher accuracy 1 Faster integration lower accuracy Individual Register Names and Addresses 1 7Fh ASE10CR0 1 7Fh ASE11CR0 1 8Fh 2L Column 7 6 5 4 3 2 1 0 Access POR RW 0 Bit Name FVal...

Page 260: ...red Note SADC_TSCMPL and SADC_TSCMPH can be combined to form a 16 bit comparison The 10 bit SAR ADC controller only exists in the CY8C28x03 CY8C28x13 CY8C28x33 CY8C28x43 and CY8C28x45 PSoC devices This register is not used for the CY8C28x23 and CY8C28x52 devices For additional information refer to the Register Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 7 0 TS_CMPL The compare...

Page 261: ...ered Note SADC_TSCMPL and SADC_TSCMPH can be combined to form a 16 bit comparison The 10 bit SAR ADC controller only exists in the CY8C28x03 CY8C28x13 CY8C28x33 CY8C28x43 and CY8C28x45 PSoC devices This register is not used for the CY8C28x23 and CY8C28x52 devices For additional information refer to the Register Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 7 0 TS_CMPH The compar...

Page 262: ...l Output Bus even bus bit 1 GOE 1 0010b Global Output Bus even bus bit 0 GOE 0 0011b Row 0 Broadcast Bus 0100b Analog Column Comparator 4 0101b Analog Column Comparator 5 0110b Analog Column Comparator 0 0111b Analog Column Comparator 1 1000b Reserved Zero 1001b Row 1 Broadcast Bus 1010b Row 2 Broadcast Bus 1011b Reserved High 1100b Analog Column Comparator 4 single synchronized 1101b Analog Colum...

Page 263: ...3 ICLKS2 ICLKS1 and ICLKS0 in the DEC_CR0 and DEC_CR1 registers 5 3 HIGH 2 0 000b The dedicated PWM is not in use The gating signal reverts to a digital block output as selected by the ICLKS bits in the DEC_CR0 and DEC_CR1 registers 001b High time is 1 VC3 period 010b High time is 2 VC3 periods 011b High time is 4 VC3 periods 100b High time is 8 VC3 periods 101b High time is 16 VC3 periods 110b Re...

Page 264: ...nd Hold Enable The sample and hold function is only applicable to the PMUX positive comparator input 0 Disabled 1 Enabled 3 CBSRC Digital Comparator Bus Source There are two possible sources for the digital comparator bus in con junction with ADC operation 0 Digital comparator bus is driven with synchronized and gated analog comparator output Implements a Counter Enable interface 1 Digital compara...

Page 265: ...written with a value of 0 For additional information see Register Definitions on page 452 in the Two Column Limited Analog System chapter 3 2 AColumn5 1 0 Clock selection for column 5 00b Variable Clock 1 VC1 01b Variable Clock 2 VC2 10b Analog Clock 4 ACLK4 11b Analog Clock 5 ACLK5 1 0 AColumn4 1 0 Clock selection for column 4 00b Variable Clock 1 VC1 01b Variable Clock 2 VC2 10b Analog Clock 4 A...

Page 266: ...ock 20 1001b Digital Basic Block 21 1010b Digital Communication Block 22 1011b Digital Communication Block 23 1100b Reserved 1101b Reserved 1110b Reserved 1111b Reserved 3 0 ACLK4 3 0 Select the clocking source for Analog Clock 4 0000b Digital Basic Block 00 0001b Digital Basic Block 01 0010b Digital Communication Block 02 0011b Digital Communication Block 03 0100b Digital Basic Block 10 0101b Dig...

Page 267: ...t 5 4 DIVCLK5 1 0 00b No divide on selected column 5 clock 01b Divide by 2 on selected column 5 clock 10b Divide by 4 on selected column 5 clock 11b Divide by 8 on selected column 5 clock 2 SYS4 0 Column 4 clock selection is controlled by ACE_CLK_CR0 1 Column 4 clock selection is SYSCLK direct 1 0 DIVCLK4 1 0 00b No divide on selected column 4 clock 01b Divide by 2 on selected column 4 clock 10b D...

Page 268: ...be output to Global Digital Output Even Bus Decimator GOO Bus Bit 0 output to GOO 0 1 output to GOO 2 2 output to GOO 4 3 output to GOO 6 2 0 DATA_IN 2 0 Used to select one decimator data input from among the following sources The x in the following entries is the corresponding decimator number 000b ACCx_CMPO the corresponding analog column compare bus output 001b BCROWx the corresponding Broadcas...

Page 269: ...KA5 from analog column 5 100b VC3 101b Preselected clock source from digital block primary outputs See DEC_CR5 110b Reserved 111b LOW Reserved 3 DEC0_EN 1 Enables decimator 0 2 0 CLK_IN0 2 0 Selects one of the following sources as decimator 0 clock 000b VC1 001b VC2 010b CLKA4 from analog column 4 011b CLKA5 from analog column 5 100b VC3 101b Preselected clock source from digital block primary out...

Page 270: ...LKA5 from analog column 5 100b VC3 101b Preselected clock source from digital block primary outputs See DEC_CR5 110b Reserved 111b LOW Reserved 3 DEC2_EN 1 Enable decimator 2 2 0 CLK_IN2 2 0 Selects one as decimator 2 clock from among the following sources 000b VC1 001b VC2 010b CLKA4 from analog column 4 011b CLKA5 from analog column 5 100b VC3 101b Preselected clock source from digital block pri...

Page 271: ...the Register Definitions on page 488 in the Decimator chapter 3 0 DSCLK 3 0 Indicate which digital block s primary output is selected as a decimator clock source Note LOW is selected when DSCLK is greater than 1011b 0000b DBC00 0001b DBC01 0010b DCC02 0011b DCC03 0100b DCB10 0101b DCB11 0110b DCC12 0111b DCC13 1000b DCC20 1001b DCC21 1010b DCC22 1011b DCC23 1100b Reserved 1101b Reserved 1110b Rese...

Page 272: ...re only valid if bit 5 is set to 1 in the GDI_O_IN register 4 GDIOICR 4 0 GIO 4 drives GOO 4 1 GIO 3 drives GOO 4 Note These selections are only valid if bit 4 is set to 1 in the GDI_O_IN register 3 GDIOICR 3 0 GIO 3 drives GOO 3 1 GIO 2 drives GOO 3 when bit 3 is 1 in GDI_O_IN register Note These selections are only valid if bit 3 is set to 1 in the GDI_O_IN register 2 GDIOICR 2 0 GIO 2 drives GO...

Page 273: ... These selections are only valid if bit 5 is set to 1 in the GDI_E_IN register 4 GDIEICR 4 0 GIE 4 drives GOE 4 1 GIE 3 drives GOE 4 Note These selections are only valid if bit 4 is set to 1 in the GDI_E_IN register 3 GDIEICR 3 0 GIE 3 drives GOE 3 1 GIE 2 drives GOE 3 Note These selections are only valid if bit 3 is set to 1 in the GDI_E_IN register 2 GDIEICR 2 0 GIE 2 drives GOE 2 1 GIE 1 drives...

Page 274: ...hese selections are only valid if bit 5 is set to 1 in the GDI_O_OU register 4 GDIOOCR 4 0 GOO 4 drives GIO 4 1 GOO 3 drives GIO 4 Note These selections are only valid if bit 4 is set to 1 in the GDI_O_OU register 3 GDIOOCR 3 0 GOO 3 drives GIO 3 1 GOO 2 drives GIO 3 Note These selections are only valid if bit 3 is set to 1 in the GDI_O_OU register 2 GDIOOCR 2 0 GOO 2 drives GIO 2 1 GOO 1 drives G...

Page 275: ...hese selections are only valid if bit 5 is set to 1 in the GDI_E_OU register 4 GDEOICR 4 0 GOE 4 drives GIE 4 1 GOE 3 drives GIE 4 Note These selections are only valid if bit 4 is set to 1 in the GDI_E_OU register 3 GDEOICR 3 0 GOE 3 drives GIE 3 1 GOE 2 drives GIE 3 Note These selections are only valid if bit 3 is set to 1 in the GDI_E_OU register 2 GDEOICR 2 0 GOE 2 drives GIE 2 1 GOE 1 drives G...

Page 276: ... is from 00 to 23 In the table note that reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 534 in the Real Time Clock chapter 5 4 HR1 1 0 Hour time decal number BCD code 3 0 HR0 3 0 Hour time units number BCD code Individual Register Names and...

Page 277: ...s from 00 to 59 In the table note that reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 534 in the Real Time Clock chapter 6 4 MIN1 2 0 Minute time decal number BCD code 3 0 MIN0 3 0 Minute time units number BCD code Individual Register Names...

Page 278: ...s from 00 to 59 In the table note that reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 534 in the Real Time Clock chapter 6 4 SEC1 2 0 Second time decal number BCD code 3 0 SEC0 3 0 Second time units number BCD code Individual Register Names...

Page 279: ...xed period interrupt source 3 2 INT_SEL 1 0 Interrupt Select 00b Interrupt per second 01b Interrupt per minute 10b Interrupt per hour 11b Interrupt per day 1 SYNCRD_EN 0 RTC_M RTC_S are read directly from their registers without buffering 1 RTC_M RTC_S reads data from its data buffer The data is latched from the real register when RTC_H is read 0 RTC_EN 0 Disable RTC function 1 Enable RTC function...

Page 280: ... written with a value of 0 For additional information see Register Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 6 3 ADC_CHS 3 0 Channel selection 0000b P0 0 0001b P0 1 0010b P0 2 0011b P0 3 0100b P0 4 0101b P0 5 0110b P0 6 0001b P0 7 1000b ACC00 1001b ACC01 1010b ACC02 1011b ACC03 1100b Muxbus0 1101b Muxbus1 1110b Vbg 1111b Reserved 2 READY 1 There is new data that has never be...

Page 281: ...er 10b The extra cycle for 7th bit conversion with add on weak Vref buffer 11b The extra cycle for 1st bit conversion with add on weak Vref buffer 5 4 TIGSEL 1 0 Auto trigger source selection 00b TGL 01b TGH 10b TG16BIT 11b TGINCMP 3 1 CLKSEL 3 0 ADC Clock Selection 000b 2 001b 4 010b 6 011b 8 100b 12 101b 16 110b 32 111b 64 0 ALIGN_EN 1 to enable auto align function The ADC will be driven by outs...

Page 282: ...ions on page 541 in the 10 Bit SAR ADC Controller chapter 7 REFSEL 0 Selects Vdd as reference 1 Selects external Vref other than Vdd See EXTREF in SADC_CR4 6 BUFEN 0 Bypass Vref buffer 1 Enable Vref buffer 5 VDBEN 1 Enable voltage doubler in ADC comparator 4 VDB_CLK 0 Select SYSCLK 4 as VDB clock 1 Select SYSLCK as VDB clock 3 FREERUN 1 ADC in FREERUN mode if ADC is not in auto align mode Individu...

Page 283: ...In the table note that reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 7 LALIGN 1 Set left justified data format 2 0 ADC_TRIM0 2 0 Sent to ADC comparator block directly Individual Register Names a...

Page 284: ... devices In the table note that reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information see Register Definitions on page 541 in the 10 Bit SAR ADC Controller chapter 7 EXTREF 0 Selects REFHI as reference input 1 Selects externally supplied reference voltage on P2 6 Individual Regis...

Page 285: ... second I2 C block is available in the CY8C28x03 CY8C28x23 CY8C28x43 and CY8C28x45 PSoC devices only For additional information see Register Definitions on page 497 in the I2C chapter 7 HwAddrEn 1 Enable hardware address comparison feature Only supports 7 bit address When you enable the hardware address comparison feature I2 C block will not support the special sys tem address definition which is ...

Page 286: ...UXCLK that drives switching on the analog mux right Amuxbus1 can be synchronized to one of four phases as listed These set tings can be used to optimize noise performance by varying the analog mux sampling point relative to the system clock 00b Synchronize to SYSCLK rising edge 01b Synchronize to delayed approximately 5 ns SYSCLK rising edge 10b Synchronize to SYSCLK falling edge 11b Synchronize t...

Page 287: ...on the setting in GDI_O_IN_CR 4 GIONOUT4 0 No connection between GIO 4 GIO 3 to GOO 4 1 Allow GIO 4 GIO 3 to drive GOO 4 depending on the setting in GDI_O_IN_CR 3 GIONOUT3 0 No connection between GIO 3 GIO 2 to GOO 3 1 Allow GIO 3 GIO 2 to drive GOO 3 depending on the setting in GDI_O_IN_CR 2 GIONOUT2 0 No connection between GIO 2 GIO 1 to GOO 2 1 Allow GIO 2 GIO 1 to drive GOO 2 depending on the ...

Page 288: ... on the setting in GDI_E_IN_CR 4 GIENOUT4 0 No connection between GIE 4 GIE 3 to GOE 4 1 Allow GIE 4 GIE 3 to drive GOE 4 depending on the setting in GDI_E_IN_CR 3 GIENOUT3 0 No connection between GIE 3 GIE 2 to GOE 3 1 Allow GIE 3 GIE 2 to drive GOE 3 depending on the setting in GDI_E_IN_CR 2 GIENOUT2 0 No connection between GIE 2 GIE 1 to GOE 2 1 Allow GIE 2 GIE 1 to drive GOE 2 depending on the...

Page 289: ...on the setting in GDI_O_OU_CR 4 GOOUTIN4 0 No connection between GIO 4 GIxO 3 to GOO 4 1 Allow GOO 4 GOO 3 to drive GIO 4 depending on the setting in GDI_O_OU_CR 3 GOOUTIN3 0 No connection between GIO 3 GIO 2 to GOO 3 1 Allow GOO 3 GOO 2 to drive GIO 3 depending on the setting in GDI_O_OU_CR 2 GOOUTIN2 0 No connection between GIO 2 GIO 1 to GOO 2 1 Allow GOO 2 GOO 1 to drive GIO 2 depending on the...

Page 290: ... on the setting in GDI_E_OU_CR 4 GOEUTIN4 0 No connection between GIE 4 GIE 3 to GOE 4 1 Allow GOE 4 GOE 3 to drive GIE 4 depending on the setting in GDI_E_OU_CR 3 GOEUTIN3 0 No connection between GIE 3 GIE 2 to GOE 3 1 Allow GOE 3 GOE 2 to drive GIE 3 depending on the setting in GDI_E_OU_CR 2 GOEUTIN2 0 No connection between GIE 2 GIE 1 to GOE 2 1 Allow GOE 2 GOE 1 to drive GIE 2 depending on the...

Page 291: ...hm 11b Reserved 5 4 Data Out Shift 1 0 00b No shift 01b One shift 10b Two shifts 11b Four shifts 3 Data Format Controls how the input data stream is interpreted by the integrator 0 A 0 1 input is interpreted as 1 1 1 A 0 1 input is interpreted as 0 1 2 0 Decimation Rate 2 0 000b Off 001b 32 010b 50 011b 64 100b 125 101b 128 110b 250 111b 256 Note If this is set to anything other than Off the digit...

Page 292: ...NABLE 7 0 Each bit controls the connection between the analog mux bus and the corresponding port pin For example MUX_CR2 3 controls the connection to bit 3 in Port 2 Any number of pins may be con nected at the same time Note that if a precharge clock is selected in the AMUX_CFG register the connection to the mux bus will be switched on and off under hardware control 0 No connection between port pi...

Page 293: ...ture both IDAC0 and IDAC1 will use the IDAC0_D register for IDAC current setting when their output enable signal is high and it will automatically switch to use IDAC1_D register for IDAC setting when their output enable signal is low 4 1 IDAC_TRIM 3 0 These signals go to PLL block and are used to trim IUNIT32 current output The default value is 1000b ideally it is 10 µA Each step will change the c...

Page 294: ...k is not driven onto a global net 1 The VC2 clock is driven onto GOE 5 4 VC1 0 The VC1 clock is not driven onto a global net 1 The VC1 clock is driven onto GOE 4 3 SYSCLKX2 0 The 2 times system clock is not driven onto a global net 1 The 2 times system clock is driven onto GOE 3 2 SYSCLK 0 The system clock is not driven onto a global net 1 The system clock is driven onto GOE 2 1 CLK24M 0 The 24 MH...

Page 295: ...e not described in the bit description section Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 469 in the Digital Clocks chapter 1 0 VC3 Input Select 1 0 Selects the clocking source for the VC3 Clock Divider 00b SYSCLK 01b VC1 10b VC2 11b SYSCLKX2 Individual Register Names and Addresses 1 DEh OSC_CR4 1 DEh 7 6 5 4 3 2 1 ...

Page 296: ...quency output from the VC3 Clock Divider will be one eighth the input frequency For additional information refer to the Register Definitions on page 469 in the Digital Clocks chapter 7 0 VC3 Divider 7 0 Refer to the OSC_CR4 register 0000 0000b Input Clock 0000 0001b Input Clock 2 0000 0010b Input Clock 3 0000 0011b Input Clock 4 1111 1100b Input Clock 253 1111 1101b Input Clock 254 1111 1110b Inpu...

Page 297: ...0b 1 95 ms 512 Hz 01b 15 6 ms 64 Hz 10b 125 ms 8 Hz 11b 1s 1 Hz Sleep Interval when SLP_EXTEND 1 00b 2s 1 2 Hz 01b 4s 1 4 Hz 10b 8s 1 8 Hz 11b 16s 1 16 Hz 2 0 CPU Speed 2 0 These bits set the CPU clock speed based on the system clock SYSCLK SYSCLK is 24 MHz by default but it can optionally be set to 6 MHz on some PSoC devices see the Architectural Descrip tion on page 81 or driven from an external...

Page 298: ...ternal Main Oscillator External Clock 0000b 24 OSC_CR1 7 4 1 1 EXTCLK OSC_CR1 7 4 1 1 0001b 24 OSC_CR1 7 4 1 2 EXTCLK OSC_CR1 7 4 1 2 0010b 24 OSC_CR1 7 4 1 3 EXTCLK OSC_CR1 7 4 1 3 0011b 24 OSC_CR1 7 4 1 4 EXTCLK OSC_CR1 7 4 1 4 0100b 24 OSC_CR1 7 4 1 5 EXTCLK OSC_CR1 7 4 1 5 0101b 24 OSC_CR1 7 4 1 6 EXTCLK OSC_CR1 7 4 1 6 0110b 24 OSC_CR1 7 4 1 7 EXTCLK OSC_CR1 7 4 1 7 0111b 24 OSC_CR1 7 4 1 8 E...

Page 299: ...P_EXTEND Extend sleep timer period SLP_EXTEND 0 OSC_CR0 register SLEEP 1 0 00b 2 ms 01b 16 ms 10b 128 ms 11b 1s SLP_EXTEND 1 OSC_CR0 register SLEEP 1 0 00b 2s 01b 4s 10b 8s 11b 16s 3 WDR32_SE Watchdog clock source selection 0 The same 32 kHz clock source as system setting default mode 1 Uses internal 32 kHz oscillator as clock source even if external 32 kHz clock source is enabled 2 EXTCLKEN Exter...

Page 300: ...per the DC electrical specifications in the PSoC device data sheet 00b POR level for 2 4 V or 3 V operation refer to the PSoC device data sheet 01b POR level for 3 0 V or 4 5 V operation refer to the PSoC device data sheet 10b POR level for 4 75 V operation 11b Reserved 3 LVDTBEN Enables reset of CPU speed register by LVD comparator output 0 Disables CPU speed throttle back 1 Enables CPU speed thr...

Page 301: ...information refer to the Register Definitions on page 523 in the POR and LVD chapter 2 PUMP Read state of pump comparator 0 Vdd is above trip point 1 Vdd is below trip point 1 LVD Reads state of LVD comparator 0 Vdd is above LVD trip point 1 Vdd is below LVD trip point 0 PPOR Reads state of Precision POR comparator only useful with PPOR reset disabled with PORLEV 1 0 in VLT_CR register set to 11b ...

Page 302: ...7 0 CAPVAL_ 7 0 Controls in binary weighted segments the capacitor trim for ADC and general analog operation This trim has a 16 1 range By default 0000b all capacitors are switched into the circuit which is the maximum capacitance 0 Switches that binary weighted capacitor segment into the circuit more capacitance 1 Switches that binary weighted capacitor segment out of the circuit less capacitance...

Page 303: ...01b Reserved 0010b Reserved 0011b Reserved 0100b DECD 0 Decimator 0 data input 0101b DECD 1 Decimator 1 data input 0110b DECD 2 Decimator 2 data input 0111b DECD 3 Decimator 3 data input 1000b ACC_CMP 0 ACC 0 compare bus 1001b ACC_CMP 1 ACC 1 compare bus 1010b ACC_CMP 2 ACC 2 compare bus 1011b ACC_CMP 3 ACC 3 compare bus 1100b Reserved 1101b Reserved 1110b ACE_CMPFF 0 ACE 0 compare bus 1111b ACE_C...

Page 304: ...l information refer to the Register Definitions on page 82 in the Internal Main Oscillator chapter 7 0 Trim 7 0 The value of this register is used to trim the Internal Main Oscillator Its value is set to the best value for the device during boot The value of these bits should not be changed 0000 0000b Lowest frequency setting 0000 0001b 0111 1111b 1000 0000b Design center setting 1000 0001b 1111 1...

Page 305: ...refer to the Register Defi nitions on page 85 in the Internal Low Speed Oscillator chapter 5 4 Bias Trim 1 0 The value of this register is used to trim the Internal Low Speed Oscillator Its value is set to the device specific best value during boot The value of these bits should not be changed 00b Medium bias 01b Maximum bias recommended 10b Minimum bias 11b Intermediate Bias About 15 higher than ...

Page 306: ...oltage Reference chapter 6 AGNDBYP If set an external bypass capacitor on AGND may be connected to Port 2 4 0 Disable 1 Enable 5 4 TC 1 0 The value of these bits is used to trim the temperature coefficient Their value is set to the best value for the device during boot The value of these bits should not be changed 3 0 V 3 0 The value of these bits is used to trim the bandgap reference Their value ...

Page 307: ...at reserved bits are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 89 in the External Crystal Oscillator ECO chapter 7 6 PSSDC 1 0 Sleep duty cycle Controls the ratios in numbers of 32 768 kHz clock periods of on time versus off time for PORLVD Ban...

Page 308: ...CATA current For additional information refer to the Register Definitions on page 82 in the Internal Main Oscillator chapter 1 0 CATA_Trim 1 0 These bits are used to tune CATA current 00b Largest CATA current reset value 11b Smallest CATA current Individual Register Names and Addresses 1 EFh IMO_TR1 1 EFh 7 6 5 4 3 2 1 0 Access POR RW 0 Bit Name CATA_Trim 1 0 Bit Name Description ...

Page 309: ... are grayed table cells and are not described in the bit description section Reserved bits should always be written with a value of 0 For additional information refer to the Supervisory ROM SROM chapter on page 49 0 Bank Selects the active Flash bank for supervisory operations No affect in User mode 0 Flash Bank 0 1 Flash Bank 1 Individual Register Names and Addresses 1 FAh FLS_PR1 1 FAh 7 6 5 4 3...

Page 310: ...ux bus 6 MuxClkGE0 Global enable connection for MUXCLK0 0 Analog mux bus clock not connected to global 1 Connect analog mux bus clock to global GOO 6 5 4 OSCMD1 1 0 When set these bits enable the analog mux bus right Muxbus1 to reset to Vss whenever the com parator trip point is reached 3 IRANGE Sets the DAC range Note that the value for the unit current is found in the PSoC data sheet 0 Low range...

Page 311: ...310 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G IDAC_CR0 1 FDh ...

Page 312: ...ws The following table lists the resources available for specific device groups While read ing the digital system section determine and keep in mind the number of digital rows that are in your device to accu rately interpret this documentation DIGITAL SYSTEM Digital Clocks From Core Digital PSoC Block Array To Analog System 8 Row Input Configuration Row Output Configuration 8 8 8 Row 1 DBC10 DBC11...

Page 313: ...GDIEOCR2 GDIEOCR1 GDIEOCR0 RW 00 1 D0h GDI_O_IN 3 2 GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 RW 00 1 D1h GDI_E_IN 3 2 GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 RW 00 1 D2h GDI_O_OU 3 2 GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW 00 1 D3h GDI_E_OU 3 2 GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOE...

Page 314: ...lect 1 0 OUTEN Output Select 1 0 RW 00 1 2Bh DCC02CR1 3 2 Function control status bits for selected function 7 0 RW 00 0 2Ch DCC03DR0 3 2 Data 7 0 00 0 2Dh DCC03DR1 3 2 Data 7 0 W 00 0 2Eh DCC03DR2 3 2 Data 7 0 00 0 2Fh DCC03CR0 3 2 Function control status bits for selected function 6 0 Enable 00 1 2Ch DCC03FN 3 2 Data Invert BCEN End Single Mode 1 0 Function 2 0 RW 00 1 2Dh DCC03IN 3 2 Data Input...

Page 315: ...its for selected function 7 0 RW 00 0 44h DBC21DR0 3 Data 7 0 00 0 45h DBC21DR1 3 Data 7 0 W 00 0 46h DBC21DR2 3 Data 7 0 00 0 47h DBC21CR0 3 Function control status bits for selected function 7 1 Enable 00 1 44h DBC21FN 3 Data Invert BCEN End Single Mode 1 0 Function 2 0 RW 00 1 45h DBC21IN 3 Data Input 3 0 Clock Input 3 0 RW 00 1 46h DBC21OU 3 AUXCLK AUXEN AUX IO Select 1 0 OUTEN Output Select 1...

Page 316: ...12 DBC11 DBC10 DCC03 DCC02 DBC01 DBC00 RW 00 LEGEND x An x before the comma in the address field indicates that this register can be read or written to no matter what bank is used R Read register or bit s Access is bit specific Refer to the Register Details chapter on page 125 for additional information R Read register or bit s W Write register or bit s Summary Table of the Digital Registers conti...

Page 317: ...316 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...

Page 318: ...onnect to all even numbered ports There are two ends to the global digital interconnect core signals and port pins An end may be configured as a source or a destination For example a GPIO pin may be configured to drive a global input or receive a global output and drive it to the package pin Globals cannot loop through a GPIO Currently there are two types of core sig nals connected to the global b...

Page 319: ... 7 GOE 5 GOE 3 GOE 1 GIE 7 GIE 5 GIE 3 GIE 1 GIO 0 GIO 2 GIO 4 GIO 6 GOO 0 GOO 2 GOO 4 GOO 6 GOO 7 GOO 5 GOO 3 GOO 1 GIO 7 GIO 5 GIO 3 GIO 1 Even Numbered Pins Odd Numbered Pins Even Numbered Pins Odd Numbered Pins GIO 7 5 3 1 GIE 7 5 3 1 DB 7 0 DBI INT 23 8 CLK32K VC3 ACMP 3 0 SYSCLKX2 VC2 VC1 GIO 6 4 2 0 GIE 6 4 2 0 GOO 7 5 3 1 GOE 7 5 3 1 GOO 6 4 2 0 GOE 6 4 2 0 SYSCLKX2 SYSCLK CLK32K Digital C...

Page 320: ...nect Block Diagram for the CY8C284xx 28 Pin Package Table 14 1 28 Pin Global Bus to Port Mapping Global Bus Ports GIO 7 0 GOO 7 0 P1 GIE 7 0 GOE 7 0 P0 P2 P0 6 GO GI P0 4 GO GI P0 2 GO GI P0 7 GO GI P0 5 GO GI P0 3 GO GI P0 1 GO GI P0 0 GO GI P1 6 GO GI P1 4 GO GI P1 2 GO GI P1 7 GO GI P1 5 GO GI P1 3 GO GI P1 1 GO GI P1 0 GO GI GIE 0 GIE 2 GIE 4 GIE 6 GOE 0 GOE 2 GOE 4 GOE 6 GOE 7 GOE 5 GOE 3 GOE...

Page 321: ... 0 P1 P3 GIE 7 0 GOE 7 0 P0 P2 P4 P0 6 GO GI P0 4 GO GI P0 2 GO GI P0 7 GO GI P0 5 GO GI P0 3 GO GI P0 1 GO GI P0 0 GO GI P2 6 GO GI P2 4 GO GI P2 2 GO GI P2 7 GO GI P2 5 GO GI P2 3 GO GI P2 1 GO GI P2 0 GO GI P4 4 GO GI P4 2 GO GI P4 5 GO GI P4 3 GO GI P4 1 GO GI P4 0 GO GI P3 6 GO GI P3 4 GO GI P3 2 GO GI P3 7 GO GI P3 5 GO GI P3 3 GO GI P3 1 GO GI P3 0 GO GI P1 6 GO GI P1 4 GO GI P1 2 GO GI P1 ...

Page 322: ... GI P1 3 GO GI P1 1 GO GI P1 0 GO GI GIE 0 GIE 2 GIE 4 GIE 6 GOE 0 GOE 2 GOE 4 GOE 6 GOE 7 GOE 5 GOE 3 GOE 1 GIE 7 GIE 5 GIE 3 GIE 1 GIO 0 GIO 2 GIO 4 GIO 6 GOO 0 GOO 2 GOO 4 GOO 6 GOO 7 GOO 5 GOO 3 GOO 1 GIO 7 GIO 5 GIO 3 GIO 1 Even Numbered Pins Odd Numbered Pins GIO 7 5 3 1 GIE 7 5 3 1 DB 7 0 DBI INT 23 8 CLK32K VC3 ACMP 3 0 SYSCLKX2 VC2 VC1 GIO 6 4 2 0 GIE 6 4 2 0 GOO 7 5 3 1 GOE 7 5 3 1 GOO 6...

Page 323: ...rability of the GDI does not allow odd and even nets to be connected however connections from N to N 1 are allowed and decided by GDI_x_IN_CR The following are examples of connections that are not possible in the PSoC devices There are a total of 16 bits that control the ability of global inputs to drive global outputs These bits are in the GDI_x_IN registers Table 14 3 enumerates the meaning of e...

Page 324: ...OU registers Table 14 5 enumerates the meaning of each bit position in either of the GDI_O_OU or GDI_E_OU registers GIE 7 GOE 0 GIE 7 GOE 0 GIE 7 GOE 7 Table 14 4 GDI_x_IN_CR Register GDI_xICR 0 0 Data source is GIx 0 1 Data source is GIx 7 GDI_xICR 1 0 Data source is GIx 1 1 Data source is GIx 0 GDI_xICR 2 0 Data source is GIx 2 1 Data source is GIx 1 GDI_xICR 3 0 Data source is GIx 3 1 Data sour...

Page 325: ...obal outputs to drive global inputs These bits are in the GDI_x_OU_CR registers Table 14 6 enumerates the mean ing of each bit position in either of the GDI_O_OU_CR or GDI_E_OU_CR registers For additional information refer to the GDI_O_OU_CR reg ister on page 273 and the GDI_E_OU_CR register on page 274 GOE 7 GIE 0 GOE 4 GIE 4 GOE 4 GIE 5 Table 14 6 GDI_x_OU_CR Register GDIxOCR 0 0 Data source is ...

Page 326: ...ructure BCrow3 BCrow2 low low low low BCrow0 BCrow1 BCrow0 BCrow1 BCrow2 BCrow0 BCrow1 BCrow3 BCrow0 BCrow2 BCrow3 BCrow1 BCrow2 BCrow3 INT 11 8 INT 15 12 INT 19 16 INT 23 20 GIO 7 0 GIE 7 0 DB 7 0 DBI INT 23 8 GOO 7 0 GOE 7 0 CLK32K VC3 ACMP 3 0 SYSCLKX2 VC2 VC1 GOE 7 0 GOO 7 0 Digital PSoC Block Row 0 GIO 7 0 GlE 7 0 BCx BCy BCz BCw previous block clk previous block data FPB TPB DB 7 0 DBI TNB F...

Page 327: ...the blocks within them need to have unique register addresses Interrupt Priority Each digital PSoC block has its own interrupt priority and vector A row s position in the array determines the relative priority of the digital PSoC blocks within the row The lower the row number the higher the interrupt priority and the lower the interrupt vector address Broadcast Each digital PSoC row has an interna...

Page 328: ... The second two are of the type communication DCC This figure shows the connections between digital blocks within a row Only the signals that pass outside the gray background box in Figure 16 1 are shown at the next level of hierarchy in Figure 16 2 In Figure 16 2 the detailed view shown in Figure 16 1 of the four PSoC block grouping has been replaced by the box in the center of the figure labeled...

Page 329: ...O 7 GOO 3 GOE 7 L3 Digital PSoC Block Row GIE 0 GlO 4 GlO 0 GlE 4 RI 0 GIE 1 GlO 5 GlO 1 GlE 5 RI 1 GIE 2 GlO 6 GlO 2 GlE 6 RI 2 GIE 3 GlO 7 GlO 3 GlE 7 RI 3 BCROW 0 BCROW DB 7 0 DBI TPB FPB AUX 3 0 DATA 15 0 CLK 15 0 TNB FNB RO 3 0 INT 3 0 BCROW 4 PSoC Block Grouping High VC3 Broadcast BC Previous Block CLK SYSCLKX2 VC1 VC2 CLK32K RO 3 0 RI 3 0 ACMP 3 0 Low Previous Block Data RI 3 RO 3 RI 2 RO 2...

Page 330: ...I Register The Row Digital Interconnect Row Input Register RDIxRI is used to control the input mux that determines which global inputs will drive the row inputs The RDIxRI Register and the RDIxSYN Register are the only two registers that affect digital PSoC row input signals All other registers are related to output signal configuration The RDIxRI register has select bits that are used to control ...

Page 331: ...or row 3 Bit 2 RI2SYN This bit controls the input synchronization for row 2 Bit 1 RI1SYN This bit controls the input synchronization for row 1 Bit 0 RI0SYN This bit controls the input synchronization for row 0 For additional information refer to the RDIxSYN register on page 180 Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x B1h RDI0SYN 3 2 RI3SYN RI2SYN RI1SYN RI0SYN RW 00 ...

Page 332: ...ols the A input of LUT 3 Bit 2 IS2 This bit controls the A input of LUT 2 Bit 1 IS1 This bit controls the A input of LUT 1 Bit 0 IS0 This bit controls the A input of LUT 0 For additional information refer to the RDIxIS register on page 181 Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x B2h RDI0IS 3 2 BCSEL 1 0 IS3 IS2 IS1 IS0 RW 00 x BAh RDI1IS 3 2 BCSEL 1 0 IS3 IS2 IS1 IS0...

Page 333: ...en examples of the relationship between the LUT s output column for a truth table and the LUTx 3 0 configuration bits Figure 16 3 on page 331 presents an example of LUT configuration Bits 7 to 4 LUTx 3 0 These configuration bits are for a row output LUT Bits 3 to 0 LUTx 3 0 These configuration bits are for a row output LUT For additional information refer to the RDIxLT0 register on page 182 and th...

Page 334: ...IxRO0 Register Bits 7 to 4 GOxxEN These configuration bits enable the tri state buffers that connect to the global output lines for LUT 1 Bits 3 to 0 GOxxEN These configuration bits enable the tri state buffers that connect to the global output lines for LUT 0 For additional information refer to the RDIxRO0 register on page 186 16 2 5 2 RDIxRO1 Register Bits 7 to 4 GOxxEN These configuration bits ...

Page 335: ...ration bits enable average function on corresponding RO channel For additional information refer to the RDIxDSM register on page 188 16 3 Timing Diagram Figure 16 4 Optional Row Input Synchronization to SYSCLK Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x B7h RDI0DSM 3 2 AVG_SEL 3 0 AVG_EN 3 0 RW 00 x BFh RDI1DSM 3 2 AVG_SEL 3 0 AVG_EN 3 0 RW 00 x C7h RDI2DSM 3 AVG_SEL 3 0...

Page 336: ...ividual PSoC block or chaining several PSoC blocks together to form functions that are greater than 8 bits Digital communications PSoC blocks have two additional functions master or slave SPI and a full duplex UART Each digital PSoC block s function is independent of all other PSoC blocks Up to eight registers are used to deter mine the function and state of a digital PSoC block These registers ar...

Page 337: ...e Table 17 1 2 If the clock input is derived from SYSCLKX2 resynchro nize to SYSCLKX2 For example VC3 clocked by SYSCLKX2 or other digital blocks clocked by SYSCLKX2 for setting see Table 17 1 3 Choose direct SYSCLK for clocking directly off of SYS CLK for setting see Table 17 1 4 Choose direct SYSCLKX2 select SYSCLKX2 in the Clock Input field of the DxCxxIN register for clocking directly off of S...

Page 338: ...ches the first 00 DR0 is reloaded and runs again The function is disabled after the second 00 in DR0 register The multi shot supports up to a MAX number of 15 shots Hardware capture occurs on the positive edge of the data input This event transfers the current count from DR0 to DR2 The captured value may then be read directly from DR2 A software capture function is equivalent to a hard ware captur...

Page 339: ...equent clocks counting continues Refer to the timing diagram for this function on page 365 17 1 7 1 Counter Timing This function also supports multi shot mode When the multi shot register is set to non zero the function is in multi shot mode For example if the multi shot register is set to 01h the function is disabled after it reaches the first 00 value in DR0 If the multi shot register is set to ...

Page 340: ...input clock or it can be clocked directly by toggling a bit in software using the Bit Bang inter face If the clock source is a PWM this will make a two out put PWM with guaranteed non overlapping outputs An active asynchronous signal on the KILL data input disables both outputs immediately The PWM with the Dead Band User Module configures one or two blocks to create an 8 or 16 bit PWM and configur...

Page 341: ...igital block output must be resynchronized through a row input before using it as a digital block input 17 1 8 2 Block Interrupt The Dead Band block has two interrupt sources The default one is the Phase 1 primary output clock When the KILL sig nal is asserted the interrupt follows the same behavior of the Phase 1 output with respect to the various KILL modes When KILL_INT is selected the KILL sig...

Page 342: ...ed to 0 then the block functions as a pseudo random sequencer PRS generator with the output data generated at the clock rate The most significant bit MSb of the CRCPRS function is the primary output The CRCPRS has a selection of compare modes between DR0 and DR2 The default behavior of the compare is DR0 DR2 When the PRS function cycles through the seed value as one of the valid counts the compare...

Page 343: ...each tap point enables the XOR with the MSb for that given bit The CRCPRS function implements the modular approach These are equivalent methods However there is a conver sion that should be understood If tables are specified in simple register format then a conversion can be made to the modular format by subtracting each tap from the MS tap as shown in the following example To implement a 7 bit PR...

Page 344: ... transfer both master and slave are transmitting and receiving simultane ously If the master is only sending data the received data from the slave is ignored If the master wishes to receive data from the slave the master must send dummy bytes to generate the clocking for the slave to send data back 17 1 11 1 SPI Protocol Signal Definitions The SPI Protocol signal definitions are located in Table 1...

Page 345: ...are usability exceptions for the SPI Protocol function 1 The MISO input must be resynchronized at the row inputs 2 The DR2 Rx Buffer register is not writeable 3 CR1 is not writeable when the SPIM is enabled 17 1 12 2 Block Interrupt The SPIM block has a selection of two interrupt sources Interrupt on TX Reg Empty default or interrupt on SPI Complete Mode bit 1 in the function register controls the...

Page 346: ...hronous Transmitter and Receiver Functions The Asynchronous Transmitter and Receiver functions are illustrated in Figure 17 6 Figure 17 6 Asynchronous Transmitter and Receiver Block Diagram 17 1 14 1 Asynchronous Transmitter Function In the Transmitter function DR0 functions as a shift register with no input and with the TXD serial data stream output to the primary output F1 DR1 is a TX Buffer reg...

Page 347: ...ck is generated subsequently sampling the RXD input at the center of the bit time Every subsequent START bit resynchronizes the clock generator to the incom ing bit rate There are two formats supported A 10 bit frame size includ ing one start bit eight data bits and one stop bit or an 11 bit frame size including one start bit eight data bits one parity bit and one stop bit The received data is an ...

Page 348: ...NOR or signal reference type through an AND One input comes from on block generated density signal Another comes from outside block through DATA selection MUX The multiplying result can go to primary out put of the block DSM function supports two types of KILL mode KILL Async or KILL Disable In KILL Async mode the block outputs are gated by KILL signal In KILL Disable mode the function is disabled...

Page 349: ...17 10 To reference timing dia grams associated with the digital block registers see Timing Diagrams on page 363 For a complete table of digital block registers refer to the Summary Table of the Digital Registers on page 312 Data and Control Registers The following table summarizes the Data and Control registers by function type for the digital blocks Table 17 10 Digital Block Data and Control Regi...

Page 350: ... when KILL is asserted When disabled a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2 This transfer only occurs in the addressed block When enabled a read of DR0 returns 00h to the data bus and synchronously transfers the contents of DR0 to DR2 It oper ates simultaneously on the byte addressed and all higher bytes in a multi block timer Note that when the hardware...

Page 351: ... this register also transfers the period value directly into DR0 When enabled if the block frequency is 24 MHz or below this register may be written to at any time but the period will only be reloaded into DR0 in the clock following a TC If the block frequency is 48 MHz the Terminal Count or Compare Interrupt should be used to synchronize the new period register write otherwise the counter can be ...

Page 352: ...s 48 MHz the Terminal Count or Compare Interrupt should be used to synchronize the new period register write otherwise the counter can be incorrectly loaded DR2 Compare Read write register DR2 functions as a Compare register When enabled the compare output is computed using the compare type set in the function register mode bits between DR0 and DR2 The result of the compare is output to the primar...

Page 353: ...pty sta tus is set DR2 RX Buffer Read only register When a byte transmission reception is complete the data in the shifter DR0 is transferred into the RX Buffer register and RX Reg Full status in the Control register is set A read from this register DR2 clears the RX Reg Full status bit in the Control register Table 17 17 SPIS Data Register Descriptions Name Function Description DR0 Shifter Not re...

Page 354: ...set The RX Reg Full status bit in the Control register is cleared when this register is read Table 17 20 DSM Data Register Descriptions Name Function Description DR0 Difference Not directly readable or writeable During normal operation DR0 stores the current value of a synchronous subtracter When disabled a write to the DR1 initial minuend register is also simultaneously loaded into DR0 from the d...

Page 355: ...s Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 xxh DxCxxCR0 Counter Control 001 3 2 KILL 3 0 NPS DR2BufEN Enable RW 00 LEGEND xx An x after the comma in the address field indicates that there are multiple instances of the register For an expanded address listing of these registers refer to the Digital Register Summary on page 312 Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 356: ...or additional information xx An x after the comma in the address field indicates that there are multiple instances of the register For an expanded address listing of these registers refer to the Digital Register Summary on page 312 Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 xxh DCCxxCR0 SPIS Con trol 1 110 4 3 2 1 LSb First Overrun SPI Com plete TX Reg Empty RX Reg Full...

Page 357: ...ion uses the previous clock primary output as the input reference 1 Function uses the Bit Bang Clock register as the input reference PWMDBL There are seven bits in the Control CR0 register one to enable the block one to set software trigger mode one to select between extending or not extending compare output half cycle and four bits for START signal selection Note The PWMDBL function does not supp...

Page 358: ...12 Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 xxh DxCxxCR1 Counter Control 001 3 2 Multi Shot KILL_INV KILL_MD 1 0 KILL_INT RW 00 LEGEND xx An x after the comma in the address field indicates that there are multiple instances of the register For an expanded address listing of these registers refer to the Digital Register Summary on page 312 Add Name Rows Bit 7 Bit 6 Bit...

Page 359: ...the comma in the address field indicates that there are multiple instances of the register For an expanded address listing of these registers refer to the Digital Register Summary on page 312 Table 17 22 DxCxxCR1 Control Register Descriptions Function Description Timer There are 8 bits in the Control CR1 register one for KILL interrupt select two to select KILL mode one to decide whether invert KI...

Page 360: ...e for row 1 block 3 Bit 6 DCC12 Digital communications block interrupt enable for row 1 block 2 Bit 5 DBC11 Digital basic block interrupt enable for row 1 block 1 Bit 4 DBC10 Digital basic block interrupt enable for row 1 block 0 Bit 3 DCC03 Digital communications block interrupt enable for row 0 block 3 Bit 2 DCC02 Digital communications block interrupt enable for row 0 block 2 Bit 1 DBC01 Digita...

Page 361: ... 222 Add Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 xxh DxCxxFN 3 2 Data Invert BCEN End Single Mode 1 0 Function 2 0 RW 00 LEGEND xx An x after the comma in the address field indicates that there are multiple instances of the register For an expanded address listing of these registers refer to the Digital Register Summary on page 312 Table 17 23 DxCxxFN Function Registers ...

Page 362: ...Enable bit is 0 the Aux IO Select bits are used to select one of four inputs from the auxiliary data input mux to drive the SS_ input Alternatively when the Aux IO Enable bit is a 1 the SS_ signal is driven directly from the value of the Aux IO Select 0 bit Thus the SS_ input can be controlled in firmware eliminating the need to use an addi tional GPIO pin for this purpose Regardless of how the SS...

Page 363: ... therefore routing SS_ from an input pin is unnecessary Bits 4 and 3 AUX IO Select 1 0 These two bits select one out of the four row outputs to drive the Auxiliary output onto In SPI Slave mode these bits are used in conjunction with the AUXEN bit to control the Slave Select SS_ signal In this mode these two bits are used to select one of four row inputs for use as SS_ If no SS_ is required in a g...

Page 364: ...e or is the least significant block in a chain the Carry Out CO signal is also asserted If the period is set to 00h and the TC Pulse Width mode is one half cycle the output is the inversion of the input clock The Compare CMP output will be asserted in the cycle follow ing the compare true and will be negated one cycle after compare false Multi shot Operation A 4 bit multi shot down counter is avai...

Page 365: ...st significant block in the chain In a chained timer the CO output indicates that the block and all lower blocks are at 00h count The CO is set up to the next positive edge of the clock to enable the next higher block to count once for every Terminal Count TC of all lower blocks The terminal count out of a given block becomes the termi nal count in of the next least significant block in the chain ...

Page 366: ...it is not closing near an edge on which the count is changing A limitation is that capture will not work with the block clock of 48 MHz A fundamental limitation to Timer Capture oper ation is the fact the GPIO inputs are currently synchronized to the 24 MHz system clock KILL Interrupt Generation KILL interrupt occurs when the function is enabled Therefore no interrupt occurs if the KILL is already...

Page 367: ... page 364 Gate Enable Operation The data input controls the counter enable The transition on this enable must have at least one 24 MHz cycle of setup time to the block clock This will be ensured if internal or synchronized external inputs are used As shown in Figure 17 15 when the data input is negated counting is disabled and the count is 00h the TC output stays low When the data input goes high ...

Page 368: ...ging the PWM Duty Cycle Under normal circumstances the dead band period is less than the minimum PWM high or low time As an example consider Figure 17 17 where the low of the PWM is four clocks the dead band period is two clocks and the high time of the PHI2 is two clocks Figure 17 17 DB High Time is PWM Width Minus DB Period Figure 17 18 illustrates the reduction of the width of the PWM low time ...

Page 369: ...n KILL is negated the next incoming PWM refer ence edge restarts dead band processing See Figure 17 20 2 Asynchronous Restart Mode When KILL is asserted high the internal state is not affected When KILL is negated the outputs are restored subject to a minimum disable time between one half and one and one half clock cycle See Figure 17 21 3 Disable Mode There is no specific timing associated with D...

Page 370: ... signal does not affect PWMDBL To ensure safe timing START is synchronized at the rising edge of the block clock See Figure 17 22 Compare Operation The Compare operation is identical to the Timer function except the polarity of compare output is swapped Note that this compare output is also the refer ence input to the integrated dead band see Figure 17 23 The dead band requires at least 2 cycles h...

Page 371: ...k Phase and Clock Polarity Clock phase indicates the relationship of the clock to the data When the clock phase is 0 it means that the data is registered as an input on the leading edge of the clock and the next data is output on the trailing edge of the clock When the clock phase is 1 it means that the next data is output on the leading edge of the clock and that data is reg istered as an input o...

Page 372: ...ser initially writes a byte to transmit when TX Reg Empty status is true If no transmission is currently in progress the data is loaded into the shifter and the transmission is initiated The TX Reg Empty status is asserted again and the user is allowed to write the next byte to be transmitted to the TX Buffer regis ter After the last bit is output if TX Buffer data is available with one half clock...

Page 373: ...terrupt and is generated when eight bits of data and clock have been sent In modes 0 and 1 this occurs one half cycle after RX Reg Full is set because in these modes data is latched on the leading edge of the clock and there is an additional one half cycle remaining to complete that clock In modes 2 and 3 this occurs at the same edge that the receive data is latched This signal may be used to read...

Page 374: ...Progress Transfer in Progress SCLK Mode 1 SCLK Mode 0 SS Transfer in Progress Transfer in Progress MODE 2 3 Phase 1 Output on leading edge Input on trailing edge SCLK Polarity 0 Mode 2 MOSI MISO SCLK Polarity 1 Mode 3 7 6 5 4 3 2 1 0 SS_ TX REG EMPTY RX REG FULL SPI COMPLETE OVERRUN Overrun occurs one half cycle before the last bit is received Last bit of byte is received All clocks and data for t...

Page 375: ... has no internal clock it must be enabled with setup time to any external master supplying the clock Setup time is also required for a TX Buffer register write before the first edge of the clock or the first falling edge of SS_ depending on the mode This setup time must be assured through the protocol and an understanding of the timing between the master and slave in a system When the block is dis...

Page 376: ...how the Shift register is loaded from the TX Buffer register All modes use the following mechanism 1 If there is no transfer in progress 2 if the shifter is empty and 3 if data is available in the TX Buffer register the byte is loaded into the shifter The only difference between the modes is that the definition of transfer in progress is slightly different between modes 0 and 1 and modes 2 and 3 F...

Page 377: ...the preceding SPIS operations are maintained the same with the following exceptions More transits for more bits Only need to enable LSB block to enable the function such as in chained Timer Counter CRCPRS PWMDBL functions Need to write MSB TX register first and then LSB regis ter to set new data Always read MSB RX data first and then LSB RX data Always check LSB status bits for whole SPIM status i...

Page 378: ...l internal state is reset including CR0 status to its configuration specific reset state except for DR0 DR1 and DR2 which are unaffected Transmit Operation Transmission is initiated with a write to the TX Buffer register DR1 The CPU write to this regis ter is required to have one half bit clock setup time for the data to be recognized at the next positive internal bit clock edge As shown in Figure...

Page 379: ... this signal initiates one subject to the timing The default interrupt in the Transmitter is tied to TX Reg Empty However an initial interrupt is not generated when the block is enabled The user must write an initial byte to the TX Buffer register That byte must be transferred into the shifter before interrupts generated from the TX Reg Empty status bit are enabled This prevents an interrupt from ...

Page 380: ...ming bit at the nominal center point This clock also sequences the state machine at the specified bit rate The sampled data is registered into an input flip flop This flip flop feeds the DR0 Shift register Only data bits are shifted into the Shift register At the STOP sample point the block is immediately within one cycle of the 24 MHz system clock set back into an idle state In this way the clock...

Page 381: ...three samples of the input clock the status RXACTIVE is asserted which initiates a reception If this sample of the RXD line is a logic 1 the input 0 transition was assumed to be a false start and the Receiver remains in the idle state Figure 17 37 shows that the internal bit clock CCLK is run ning slower than the external TX bit clock and the STOP bit is sampled later than the actual center point ...

Page 382: ... indicates a byte has been received and trans ferred into the RX Buffer register This status bit is cleared when the user reads the RX Buffer register DR2 The set ting of this bit is synchronized to the STOP sample point This is the earliest point at which the Framing Error status can be set and therefore error status is defined to be valid when RX Reg Full is set RX Active can be polled to determ...

Page 383: ...o Timer Counter but looser because it is only single block function KILL Operation DSM supports two KILL modes KILL Disable and KILL_Async KILL Disable is same as Timer Counter KILL Disable KILL Async is same as Dead Band KILL Async mode CCLK IDLE START BIT0 STATE BIT1 BIT5 BIT6 BIT7 STOP RXD D0 D6 D7 D1 RX_REG_FULL PARITY_ERROR FRAMING_ERROR RX_ACTIVE IDLE All status except Overrun is set synchro...

Page 384: ...on page 441 Top Level Analog Architecture The following figures show the analog system architecture for each of the CY8C28xxx subfamilies in detail Note that the CY8C28x03 devices have no analog blocks With the exception of the analog drivers each component of the fig ure is discussed at length in this section Analog System Block Diagram for CY8C28x13 Devices The CY8C28x13 device group has limited...

Page 385: ... outputs and four analog columns ACC00 ACC01 Block Array Array Input Configuration ACI1 1 0 ASD20 ACI0 1 0 P0 6 P0 4 P0 2 P0 0 P2 6 P2 4 RefIn AGNDIn P0 7 P0 5 P0 3 P0 1 P2 3 P2 1 Reference Generators AGNDIn RefIn Bandgap RefHi RefLo AGND ASD11 ASC21 ASC10 Interface to Digital System M8C Interface Address Bus Data Bus Etc Analog Reference ACC00 ACC01 Block Array Array Input Configuration ACI1 1 0 ...

Page 386: ...s analog input on all GPIO It has four analog outputs and four analog columns ACC00 ACC01 Block Array Array Input Configuration ACI1 1 0 ACI2 1 0 ACC02 ACC03 ASC12 ASD13 ASD22 ASC23 ASD20 ACI0 1 0 ACI3 1 0 P0 6 P0 4 P0 2 P0 0 P2 2 P2 0 P2 6 P2 4 RefIn AGNDIn P0 7 P0 5 P0 3 P0 1 P2 3 P2 1 Reference Generators AGNDIn RefIn Bandgap RefHi RefLo AGND ASD11 ASC21 ASC10 Interface to Digital System M8C In...

Page 387: ...alog input on all GPIO They have four analog outputs and six analog columns ACC00 ACC01 Block Array Array Input Configuration ACI1 1 0 ACI2 1 0 ACC02 ACC03 ASC12 ASD13 ASD22 ASC23 ASD20 ACI0 1 0 ACI3 1 0 P0 6 P0 4 P0 2 P0 0 P2 2 P2 0 P2 6 P2 4 RefIn AGNDIn P0 7 P0 5 P0 3 P0 1 P2 3 P2 1 Reference Generators AGNDIn RefIn Bandgap RefHi RefLo AGND ASD11 ASC21 ASC10 Interface to Digital System M8C Inte...

Page 388: ...n from neighboring analog blocks or various voltage reference sources The analog blocks are organized into columns Each column contains one Continuous Time CT block Type C ACC one Switched Capacitor SC block Type C ASC and one Switched Capacitor block Type D ASD However the number of analog columns in a specific part can either be 0 2 or 4 columns To determine the number of columns in your PSoC de...

Page 389: ...l to Analog Converters Programmable Gain Loss Stage Analog Comparators Zero Crossing Detectors Sample and Hold Low Pass Filter Band Pass Filter Notch Filter Amplitude Modulators Amplitude Demodulators Sine Wave Generators Sine Wave Detectors Sideband Detection Sideband Stripping Temperature Sensor Audio Output Drive DTMF Generator FSK Modulator Embedded Modem By modifying registers as described in...

Page 390: ... SARCNT 2 0 SARSIGN SARCOL 1 0 SYNCEN RW 00 0 66h CMP_CR1 4 CLDIS 3 CLDIS 2 CLDIS 1 CLDIS 0 RW 00 2 CLDIS 1 CLDIS 0 CLK1X 1 CLK1X 0 0 E6h DEC_CR0 4 2 IGEN 3 0 ICLKS0 DCOL 1 0 DCLKS0 RW 00 0 E7h DEC_CR1 4 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 RW 00 2 ECNT IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 1 60h CLK_CR0 4 AColumn3 1 0 AColumn2 1 0 AColumn1 1 0 AColumn0 1 0 RW 00 2 AColumn1 1 0 ...

Page 391: ...PWR RW 00 1 7Fh ASE10CR0 4 FVal RW 00 1 83h ACE_AMD_CR1 4 AMOD1 3 0 RW 00 1 85h ACE_PWM_CR 4 HIGH 2 0 LOW 1 0 PWMEN RW 00 1 86h ACE_ADC0_CR 4 CMPST LOREN SHEN CBSRC AUTO ADCEN 00 1 87h ACE_ADC1_CR 4 CMPST LOREN SHEN CBSRC AUTO ADCEN 00 1 89h ACE_CLK_CR0 4 AColumn1 1 0 AColumn0 1 0 RW 00 1 8A ACE_CLK_CR1 4 ACLK1 3 0 ACLK0 3 0 RW 00 1 8Bh ACE_CLK_CR3 4 SYS1 DIVCLK1 1 0 SYS0 DIVCLK0 1 0 RW 00 1 8Dh A...

Page 392: ...BMuxSD PWR 1 0 RW 00 0 90h ASD20CR0 4 2 FCap ClockPhase ASign ACap 4 0 RW 00 0 91h ASD20CR1 4 2 AMux 2 0 BCap 4 0 RW 00 0 92h ASD20CR2 4 2 AnalogBus CompBus AutoZero CCap 4 0 RW 00 0 93h ASD20CR3 4 2 ARefMux 1 0 FSW1 FSW0 BSW BMuxSD PWR 1 0 RW 00 0 98h ASD22CR0 4 FCap ClockPhase ASign ACap 4 0 RW 00 0 99h ASD22CR1 4 AMux 2 0 BCap 4 0 RW 00 0 9Ah ASD22CR2 4 AnalogBus CompBus AutoZero CCap 4 0 RW 00...

Page 393: ...392 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...

Page 394: ...1 displays the top level diagram of the PSoC device s analog interface system Figure 18 1 Analog Comparator Bus Slice Latch CMP CBUS Driver Transparent PHI1 or PHI2 Latch PHI2 BYPASS CLDIS CMP_CR1 7 4 To Col i 1 LUT From Col i 1 IGEN 1 0 Incremental Gate One per Column From Digital Blocks Destinations 1 Comparator Register 2 Data Inputs for Digital Blocks 3 Input to Decimator Column Interrupt PHI2...

Page 395: ...own in Figure 18 1 the comparator bus output is gated by the primary output of a selected digital block This feature is used to precisely control the integration period of an incre mental ADC Any digital block can be used to drive the gate signal This selection may be made with the ICLKS bits in registers DEC_CR0 and DEC_CR1 This function may be enabled on a column by column basis by setting the I...

Page 396: ... the analog array and analog clock generation circuitry to the decimator block 1 CD Comparator Data 2 CLK2X Selected analog column s 2x clock 3 CLK Selected analog column s 1x clock 4 BW The source for the decimator data input CD is selected from any of the four column comparator outputs plus several other sources After the source column is selected the two clocks associated with that column CLK2X...

Page 397: ... When the SYNCEN bit is set an I O write instruction to any Switch Capacitor register is blocked at the interface and the CPU will stall On the subsequent rising edge of PHI1 the CPU stall is released allowing the I O write to be performed at the destination analog register This mode synchronizes the I O write action to perform at the optimum point in the analog cycle at the expense of CPU bandwid...

Page 398: ...ect the previous bit guess based on the current comparator value To set the next guess next least significant bit The CPU latches this SAR modified data ORs it with 0 no CPU modification and writes it back to the DAC register A counter in the SAR hardware is used to decode which bits are being operated on in each cycle In this way the capa bility of the CPU and the IOR IOW control lines are used t...

Page 399: ...y value other than 0 an IOR command to an SC block is assumed to be part of a SAR sequence Assuming the comparator bus output is programmed for col umn 0 a typical firmware sequence is as follows mov reg ASY_CR 60h SAR count value 6 Sign 0 Col 0 or reg ASC10CR0 0 Check sign set bit 4 or reg ASC10CR0 0 Check bit 4 set bit 3 or reg ASC10CR0 0 Check bit 3 set bit 2 or reg ASC10CR0 0 Check bit 2 set b...

Page 400: ...summing voltage is opposite to that of the input volt age this triggers a Clear of the previous bit set By defi nition the final result of the summing voltage is less than one LSb from AGND therefore clearing the LSb will result in a summing voltage of the same polarity as the input voltage According to number 2 above the sign bit of the LS block can be handled exactly as the sign bit of the MS bl...

Page 401: ...see the Cols column in the register tables below only cer tain bits are accessible to be read or written refer to the table titled PSoC Device Characteristics on page 387 The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow Reserved bits should always be written with a value of 0 18 3 1 CLK_CR3 Register The Analog Clock...

Page 402: ...s ing interrupt signal Firmware can use this capability to syn chronize to the current column clock Bits 7 to 4 COMP x These bits are the read only bits cor responding to the comparator bits in each analog column They are synchronized to the column clock and thus may be reliably polled by the CPU Bits 3 to 0 AINT x These bits select the interrupt source for each column as the input to the interrup...

Page 403: ...t 4 set bit 3 or reg ASC10CR0 0 Check bit 3 set bit 2 or reg ASC10CR0 0 Check bit 2 set bit 1 or reg ASC10CR0 0 Check bit 1 set bit 0 or reg ASC10CR0 0 Check bit 0 Bit 3 SARSIGN This bit is the SAR sign selection and optionally inverts the comparator input to the SAR accelera tor It must be set based on the type of PSoC block configu ration selected Table 18 5 lists some typical examples Bits 2 an...

Page 404: ...tput is only processed for the precise conver sion time The digital block selected for the gating function is controlled by ICLKS0 in this register and ICLKS3 ICLKS2 and ICLKS1 bits in the DEC_CR1 register Bit 3 ICLKS0 In conjunction with ICLKS1 ICLKS2 and ICLKS3 in the DEC_CR1 register these bits select up to one of 16 digital blocks depending on the PSoC device resources to provide the gating si...

Page 405: ... for each col umn The bits in this register select the source for each col umn clock generator depending on how many analog columns are supported in your PSoC device Regardless of the source selected the input clock is divided by four to gen erate the PHI1 PHI2 non overlapping clocks for the column There are four selections for each clock VC1 VC2 ACLK0 and ACLK1 VC1 and VC2 are the programmable gl...

Page 406: ...e PHI2s Bits 5 to 0 ACLKx 2 0 There are two 3 bit fields in this register that can select up to one of twelve digital blocks depending on the PSoC device resources to function as the clock source for ACLK0 and ACLK1 ACLK0 and ACLK1 are alternative clock inputs to the analog column clock gen erators see the CLK_CR0 register above For additional information refer to the CLK_CR1 register on page 237 ...

Page 407: ...ister The Comparator Bus to Global Outputs Enable Register 1 CMP_GO_EN1 controls options for driving the analog comparator bus and column clock to the global bus This register is only used by the CY8C28x43 CY8C28x45 and CY8C28x52 PSoC devices Bit 7 GOO7 This bit drives the selected column 3 signal to GOO7 Bit 6 GOO3 This bit drives the selected column 3 signal to GOO3 Bits 5 and 4 SEL3 1 0 These b...

Page 408: ...applies to the next most significant neighbor column Column 0 settings apply to combinations of column 0 and column 1 Column 1 settings apply to combinations of column 1 and column 2 where B 0 for one column PSoC devices Bits 7 to 4 LUT1 3 0 These bits control the selection of the LUT 1 logic functions that may be selected for the ana log comparator bits in column 0 for two and four column PSoC de...

Page 409: ...This register can only be used with four column PSoC devices Bit 3 ACLK1R This bit selects bank one of eight digital blocks and is only used in devices with more than eight digi tal blocks Bit 0 ACLK0R This bit selects bank zero of eight digital blocks and is only used in devices with more than eight digi tal blocks For additional information refer to the CLK_CR2 register on page 245 Add Name Cols...

Page 410: ...ons for the various PSoC devices which vary depending on column availability Figure 19 1 displays the various analog arrays depending on the column configuration of the PSoC device Each ana log column has 3 analog blocks associated with it In the fig ures throughout this chapter shading and call outs portray the different column configurations that are available in a PSoC device Note The CY8C28x03...

Page 411: ...row are the corresponding NMux select line values for the data in the NMux portion of the register The call out names in the figure show nets selected for each NMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column functional ity and gray call outs and arrows signify commona...

Page 412: ...the corresponding PMux select line values for the data in the PMux portion of the register The call out names in the figure show nets selected for each PMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column functional ity and gray call outs and arrows signify commonality wit...

Page 413: ...nation of the RBot Mux bits ACC0xCR0 bits 1 and 0 and the INSAMP bit ACC0xCR3 bit 1 For example the RBotMux selects a connection to AGND if the INSAMP bit is low and the RBot Mux bits are 01b This is shown in the figure as the logic statement For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive...

Page 414: ...Figure 19 5 which are associated with each arrow are the corresponding AMux select line values for the data in the ACMux portion of the register The call out names in the figure show nets selected for each AMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column functional ity...

Page 415: ...locks These blocks are named ASC10 ASC21 ASC12 and ASC23 The CMux connections are described in detail in the ASCxxCR1 register on page 162 bits ACMux 2 0 The numbers in the figure which are associated with each arrow are the corresponding CMux select line values for the data in the CMux portion of the register The call out names in the figure show nets selected for each CMux value Note The CMux co...

Page 416: ...e 19 7 which are associated with each arrow are the corresponding BMux select line values for the data in the BMux portion of the register The call out names in the figure show nets selected for each BMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column functional ity and g...

Page 417: ...E analog comparator buses in the CY8C28x13 CY8C28x33 CY8C28x45 and CY8C28x52 devices 19 2 Temperature Sensing Capability A temperature sensitive voltage derived from the bandgap sensing on the die is buffered and available as an analog input into the Analog Switch Cap Type C block ASC21 Tem perature sensing allows protection of device operating ranges for fail safe applications Temperature sensing...

Page 418: ...and ABF_CR0 registers Edge columns in the four column configuration are fed by one of two 4 to 1 muxes inner columns are fed by one of two 4 to 1 muxes The muxes are CMOS switches with typical resistances in the range of 2K ohms Refer to the analog block diagrams on the following pages to view the various analog input configurations For a four analog column device the PSoC device has four analog d...

Page 419: ...s Data Bus Etc Interface to Digital System P0 5 P0 7 P0 1 P0 3 P1 5 P1 7 P1 1 P1 3 P2 5 P2 7 P2 1 P2 3 P3 5 P3 7 P3 1 P3 3 P4 5 P4 7 P4 1 P4 3 P5 1 P5 3 P0 4 P0 2 P0 0 P1 6 P1 4 P1 2 P1 0 P2 6 P2 4 P2 2 P2 0 P3 6 P3 4 P3 2 P3 0 P4 6 P4 4 P4 2 P4 0 P5 2 P5 0 RefIn AGNDIn 44 Pin Part 28 Pin Part 20 Pin Part P0 6 ACOL1MUX Array Array Input Configuration ACI3 1 0 ACOL2MUX ACI2 1 0 ACOL0MUX ACOL3MUX AC...

Page 420: ...log mux bus into the analog array 20 2 1 AMX_IN Register The Analog Input Select Register AMX_IN controls the analog muxes that feed signals in from port pins into the analog column This register can only be used with four and two column PSoC devices Bits 7 to 0 ACIx 1 0 For four column PSoC devices each of the analog columns can have up to four port bits connected to its muxed input There are up ...

Page 421: ...ormation refer to the ABF_CR0 register on page 238 20 2 3 AMUX_CFG1 Register Bit 7 ABusMux3 0 Select analog column 3 input to ana log column 3 mux output Selects among P0 6 4 2 0 1 Select analog column 3 input to the analog mux bus right Bit 6 ABusMux2 0 Select analog column 2 input to ana log column 2 mux output Selects among P0 7 5 3 1 1 Select analog column 2 input to the analog mux bus left Bi...

Page 422: ...nalog blocks and separately buffered within each block Note that there may be a small offset volt age between buffered analog grounds RefHi and RefLo sig nals are generated buffered and routed to the analog blocks RefHi and RefLo are used to set the conversion range that is span of analog to digital ADC and digital to analog DAC converters RefHi and RefLo can also be used to set thresholds in comp...

Page 423: ...e low bias level At high bias the analog block opamps have a faster slew rate but slightly less voltage swing and higher power Bits 5 to 3 REF 2 0 REF AGND RefHI and RefLO sets the analog array reference control selecting specific combinations of voltage for analog ground and references Many of these reference voltages are based on the preci sion internal reference a silicon bandgap operating at 1...

Page 424: ... System 001b P2 4 2 2 V P2 4 P2 6 3 2 V P2 4 P2 6 1 2 V User Adjustable Example P2 4 2 2 V and P2 6 1 0 V 010b Vdd 2 2 5 V 1 65 V Vdd 5 0 V 3 3 V Vss 0 0 V 0 0 V 5 0 V System 3 3 V System 011b 2 Vbg 2 6 V 3 Vbg 3 9 V 1 Vbg 1 3 V Not for 3 3 V Systems 100b 2 Vbg 2 6 V 2 Vbg P2 6 3 6 V 2 Vbg P2 6 1 6 V P2 6 Vdd 2 6 V Example P2 6 1 0 V 101b P2 4 2 2 V P2 4 Vbg 3 5 V P2 4 Vbg 0 V User Adjustable Exam...

Page 425: ...424 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Analog Reference ...

Page 426: ...n the control registers that determine the sig nal topology inside the block There is also a precision resistor string located in the feedback path of the opamp which is controlled by register bit settings The block also contains a low power comparator connected to the same inputs and outputs as the main amplifier This comparator is useful for providing a digital compare output in low power sleep ...

Page 427: ... bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow Reserved bits should always be written with a value of 0 In the tables below an x before the comma in the address field in the Add column indicates that the register exists in both register banks The register naming convention for arrays of PSoC blocks and their register...

Page 428: ...main opamp comparator The low power comparator is used in applications where low power is more important than low noise and low offset The low power comparator operates when the LPCMPEN bit is set high Because the main opamp comparator s output is connected to the low power comparator s output only one of the comparators should be active at a particular time The main opamp comparator is powered do...

Page 429: ... which tap is selected See the ACCxxCR0 register for details The EXGAIN bit enables additional resistor tap selections for RtapMux 0001b and RtapMux 0000b see Figure 22 4 For additional information refer to the ACCxxCR3 register on page 156 Figure 22 4 CT Block in Gain Configuration NON RB RA INV RA RB PHI1 1st CT Block 2nd CT Block INSAMP 1st ABUS 2nd ABUS PHI2 CMOUT INSAMP CMOUT PHI2 PHI1 PHI1 P...

Page 430: ...nding on the address of the registers in the above table in the Add column these registers are used for four or two column PSoC devices in the Cols column Bit 7 AnalogBus This bit controls the analog output bus ABUS A CMOS switch connects the opamp output to the analog bus Bit 6 CompBus This bit controls a tri state buffer that drives the comparator logic If no block in the analog column is drivin...

Page 431: ...MUXEN bit is high then the value of TestMux 1 0 determines which test mux input is con nected to the ABUS for that particular continuous time block If the TMUXEN bit is low then none of the test mux inputs are connected to the ABUS regardless of the value of Test Mux 1 0 Bits 3 and 2 TextMux 1 0 These bits select which signal is connected to the analog bus Bits 1 and 0 PWR 1 0 Power is encoded to ...

Page 432: ...es controlled by bit settings in control registers set the capacitor topology inside the block A group of muxes are used for the signal processing and switch synchronously to clocks PHI1 and PHI2 with behavior that is modified by con trol register settings There is also an analog comparator that converts the opamp output relative to the local analog ground into a digital signal There are two types...

Page 433: ...witch Cap Type C PSoC Blocks 1 FSW0 1 AutoZero BMuxSC BQTA P ABU S C Inputs CCa p BCap ACap 0 1 30 31 C FCap 16 32 C 2 AutoZero 1 AutoZero 2 AutoZero FSW1 Powe r AnalogBus 2B 1 ASign ARefMux OUT 2 1 RefHi RefLo AGND ACMux A Inputs B Inputs CBUS CBUS Driver 0 1 30 31 C 0 1 30 31 C Modulation Inputs Mod Bit Control 2 2 1 Comparator ...

Page 434: ...and four column PSoC devices the local connection of BQTAP is between horizontal neighbor ing SC blocks within an analog bi column For one column PSoC devices the local connection of BQTAP is vertical between the SC blocks Because the input of SC Block C ASCxx has this additional switched capacitor it is config ured for the input stage of such a switched capacitor bi quad filter When followed by a...

Page 435: ...the Cols column in the register tables below only cer tain bits are accessible to be read or written The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow Reserved bits should always be written with a value of 0 Figure 23 3 applies to the ACap BCap and CCap functionality for the capacitor registers The XCap field is used...

Page 436: ...nce This design prevents the output bus from being perturbed by the intermediate states of the SC operation often a reset state for PHI1 and settling to the valid state during PHI2 The following are the exceptions 1 If the ClockPhase bit in CR0 for the SC block in ques tion is set to 1 then the output is enabled for the whole of PHI2 2 If the SHDIS signal is set in bit 6 of the Analog Clock Source...

Page 437: ... the block output is gated by sampling clock on the last part of PHI2 If the ClockPhase bit is 1 the block output continuously drives the ABUS Bit 6 CompBus This bit controls the output to the column comparator bus CBUS Note that if the CBUS is not driven by anything in the column it is pulled low The comparator output is evaluated on the rising edge of internal PHI1 and is latched so it is availa...

Page 438: ...tch is always dis abled If the FSW1 bit is set to 1 the AutoZero bit determines the state of the switch If the AutoZero bit is 0 the switch is enabled at all times If the AutoZero bit is 1 the switch is enabled only when the internal PHI2 is high Bit 4 FSW0 This bit is used to control a switch in the inte grator capacitor path It connects the output of the opamp to analog ground Bits 3 and 2 BMuxS...

Page 439: ...acitance This design prevents the output bus from being perturbed by the intermediate states of the SC operation often a reset state for PHI1 and settling to the valid state during PHI2 The following are the exceptions 1 If the ClockPhase bit in CR0 for the SC block in ques tion is set to 1 then the output is enabled for the whole of PHI2 2 If the SHDIS signal is set in bit 6 of the Analog Clock S...

Page 440: ...last part of PHI2 If the ClockPhase bit is 1 the block ClockPhase continuously drives the ABUS Bit 6 CompBus This bit controls the output to the column comparator bus CBUS Note that if the CBUS is not driven by anything in the column it is pulled low The comparator output is evaluated on the rising edge of internal PHI1 and is latched so it is available during internal PHI2 Bit 5 AutoZero This bit...

Page 441: ...itch is enabled only when the internal PHI2 is high Bit 4 FSW0 This bit is used to control a switch in the inte grator capacitor path It connects the output of the opamp to analog ground Bit 3 BSW This bit is used to control switching in the B branch If disabled the B capacitor branch is a continuous time branch such as the C branch of the SC A Block If enabled then on internal PHI1 both ends of t...

Page 442: ...described in the I O Analog Multiplexer chapter on page 525 A summary of the I O Analog Multiplexer registers are located in the section called System Resources on page 461 24 1 Architectural Description 24 1 1 Analog Interface Figure 24 1 displays the top level diagram of the PSoC devices analog interface system Figure 24 1 Analog Comparator Bus Slice of the CY8C28xxx PSoC Devices AMP CBUS Driver...

Page 443: ...ation is set in two control registers ACE_ALT_CR0 and ACE_ALT_CR1 Each selection for each column is encoded in four bits The function value cor responding to the bit encoding is shown in Table 24 2 24 1 1 2 Analog Column Clock Generation The input clock source for each column clock generator is selectable according to the ACE_CLK_CR0 register There are four selections for each column VC1 VC2 ACLK4...

Page 444: ...al Count of the PWM can be used as a consistent interrupt to read the result of the previous conversion If only a single conversion is desired the com parator trip point can be used as an interrupt to signal the end of conversion A trim register ADCx_TR is provided for each column The converter must be calibrated for a given maximum voltage resolution and frequency of operation before use Figure 2...

Page 445: ...n basis 24 1 1 5 Analog Modulator Interface Mod Bits The Analog Modulator Interface provides a selection of sig nals that are routed to either of the two analog array modula tion control signals There is one modulation control signal for the CY8C28xxx Switched Capacitor block There are nine selections which include the dedicated reference volt age generator PWM output the analog comparator bus out...

Page 446: ...a zero is driven to the comparator block Refer to the ACCxxCR1 register on page 159 and the Analog Compara tor Bus Interface on page 442 in the Analog Interface sec tion for more information Figure 24 4 Array of Limited Analog PSoC Block 24 1 2 1 NMux Connections The NMux is an 8 to 1 mux which determines the source for the inverting also called negative input of Continuous Time CT PSoC blocks The...

Page 447: ...e sensing allows protection of device operating ranges for fail safe applications Temperature sensing combined with a long sleep timer interval to allow the die to approximate ambient temperature can give an approximate ambient temperature for data acquisition and battery charging appli cations The user may also calibrate the internal tempera ture rise based on a known current consumption The temp...

Page 448: ...ASE10CR0 ACE_AMOD_CR0 ASE10 SHEN 1 Open AUTO ENADC AMOD0 CAPVAL PWM FVAL ENADC LOREN ACE00 PMux NMux PWR CompBus ACE00CR1 ACE00CR2 VC1 VC2 AC0 AC1 SYSCLK 1 2 4 8 Column CLK0 CLK0 GIO4 GIO0 Comp0Out Sync CLDIS0 ACE_CMP_CR1 LUT0 ACE_ALT_CR0 IGEN0 DEC_CR0 PWM CompBusOutput0 COMP0 To Decimator Blocks CBSRC ACE_ADCx_CR PWM AINT0 ACE_CMP_CR0 ColumnInterrupt 0 1 2 3 Sync 1 0 1 0 PWM 1 0 1 0 AColumnx ACE_...

Page 449: ...0 7 P0 5 P0 3 P0 1 44 Pin Part 28 Pin Part Bandgap Vdd Vss VBG Reference Generators Microcontroller Interface Address Bus Data Bus Etc Interface to Digital System Analog Mux Bus P1 6 P1 4 P1 2 P1 0 P1 7 P1 5 P1 3 P1 1 P2 7 P2 5 P2 3 P2 1 P3 7 P3 5 P3 3 P3 1 P4 5 P4 3 P4 1 ACE00 ACE01 ASE10 ASE11 Array ACE1MUX Array Input Configuration ACI4 1 0 ACI5 1 0 ACM4 ACM5 AC5 P2 6 P2 4 P2 2 P2 0 P3 6 P3 4 P...

Page 450: ...d Analog Pin Block Diagram for the CY8C28xxx P0 6 P0 4 P0 2 P0 0 ACE00 ACE01 ASE10 ASE11 Array P0 7 P0 5 P0 3 P0 1 16 and Higher Pin Part 8 Pin Part Array Input Configuration Bandgap Vdd Vss VBG Reference Generators Microcontroller Interface Address Bus Data Bus Etc Interface to Digital System ACE1MUX ACI4 1 0 ACI5 1 0 ACM4 ACM5 AC5 ACE0MUX ...

Page 451: ...parator select any NMux choice except feedback FB To enable the comparator bus output the CompBus signal must be set in the ACE0xCR1 register See Figure 24 10 There are two discrete outputs from this block These out puts connect to the following buses 1 The comparator bus CBUS which is a digital bus that is a resource shared by all of the analog blocks in a col umn for that block This output is av...

Page 452: ...mparator bus 2 In the CY8C28xxx PSoC devices the switched capacitor SC block consists of a low power integrator that is enabled whenever the CT block is enabled It can be used to create a DAC reference for a CT comparator The only configuration of the internal state of the SC block available to the user is input and output connec tions and integrator speed by way of the FCap register bit 3 The CY8...

Page 453: ...s Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access POR Value ANALOG INTERFACE REGISTERS page 453 0 E6h DEC_CR0 ACC_IGEN 3 0 ICLKS 0 ACE_IGEN 2 0 DCLKS 0 RW 00 0 E7h DEC_CR1 IDEC ICLKS0 3 ICLKS0 2 ICLKS0 1 DCLKS 3 DCLKS 2 DCLKS 1 RW 00 1 E5h ADC0_TR CAPVAL_ 7 0 RW 00 1 E6h ADC1_TR CAPVAL_ 7 0 RW 00 CY8C28XXX REMAPPING PSoC BLOCK TYPE E REGISTERS page 454 1 73h ACE_AMD_CR...

Page 454: ...mer signal to sample the current decimator value to an output register that may subsequently be read by the CPU This timer period is set to be a function of the DELSIG conversion time and may be selected from up to one of twelve digital blocks depend ing on the PSoC device resources with DCLKS0 in this reg ister and DCLKS3 DCLKS2 and DCLKS1 in the DEC_CR1 register If the Decimation Rate bits are s...

Page 455: ...AMOD4 3 0 These bits control the selection of the MODBITs for analog column 4 The MODBIT is a modulated data stream input into a Switched Capacitor block Three bits for each column allow a one of eight selec tion for the MODBIT Sources include any of the analog col umn comparator buses two global buses and one broadcast bus The default for this function is zero or off For additional information re...

Page 456: ...s typically used to allow a continuous time comparator result to propagate directly to the interrupt controller during sleep Because the master clocks except the 32 kHz clock are turned off dur ing sleep the synchronizer must be bypassed For additional information refer to the ACE_CMP_CR1 reg ister on page 252 24 3 9 ACE_CMP_GI_EN Register The Comparator Bus to Global Input Enable Register con tro...

Page 457: ...x output Bit 6 ACE0Mux When set this bit sets column 4 input to column 5 input mux output For additional information refer to the ACE_ABF_CR0 reg ister on page 255 Continuous Time PSoC Block Registers 24 3 12 ACExxCR1 Register The Analog Continuous Time Type E Block Control Register 1 is one of two registers used to configure the type E contin uous time PSoC block Bit 6 CompBus This bit determines...

Page 458: ...hed capacitor PSoC block Bit 7 FVal This bit controls the size of the bandwidth of the filler in the Type E block For additional information refer to the ASExxCR0 register on page 258 24 3 15 ACE_AMD_CR1 Register The Type E Analog Modulation Control Register 1 is used to select the modulator bits used with each column Bits 3 to 0 AMOD1 3 0 These bits control the selection of the MODBITs for analog...

Page 459: ...C3 period the high time will normally be in powers of two For example in an 8 bit conversion the PWM ADC will be set for 256 clocks rather than 255 and this gives an extra code of 0 to 256 For the 256th code the 8 bit counter value will roll over and therefore be indistinguishable from code 0 However the CMPST bit will indicate that this is actually the 256th code Bit 6 LOREN This bit controls the...

Page 460: ...ow output for Type E column clocks For additional information refer to the ACE_CLK_CR1 reg ister on page 265 24 3 20 ACE_CLK_CR3 Register The Type E Analog Clock Source Control Register 3 con trols additional options for analog column clock generation It allows an option for selecting SYSCLK directly as the col umn clock source as well as additional divide values on the selected source Bit 6 SYS5 ...

Page 461: ...460 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Two Column Limited Analog System ...

Page 462: ... devices do not support the Decimator system resource All other PSoC devices support all the sys tem resources found in this section PSoC System Resources Interpreting the System Resources Documentation Information in this section covers all PSoC devices with a base part number of CY8C28xxx The following table lists the resources available for specific device groups with a check mark or appropriat...

Page 463: ...alog 0 V Monitor RW 00 2 Cols VC3 Sleep GPIO Analog 1 Analog 0 V Monitor RW 00 1 DDh OSC_GO_EN SLPINT VC3 VC2 VC1 SYSCLKX2 SYSCLK CLK24M CLK32K RW 00 1 DEh OSC_CR4 VC3 Input Select 1 0 RW 00 1 DFh OSC_CR3 VC3 Divider 7 0 RW 00 1 E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep 1 0 CPU Speed 2 0 RW 00 1 E1h OSC_CR1 VC1 Divider 3 0 VC2 Divider 3 0 RW 00 1 E2h OSC_CR2 PLLGAIN SLP_EXTE ND WDR32_SE EXTCLK...

Page 464: ...00 1 AEh I2C1_ADDR HwAddrEn Addr 6 0 RW 00 INTERNAL VOLTAGE REFERENCE REGISTER page 511 1 EAh 4 2 Cols BDG_TR AGNDBYP TC 1 0 V 3 0 RW 00 SYSTEM RESET REGISTERS page 514 0 FEh CPU_SCR1 IRESS SLIMO ECO EXW ECO EX IRAMDIS 00 0 FFh CPU_SCR0 GIES WDRS PORS Sleep STOP XX POR AND LVD REGISTERS page 523 1 E3h 4 2 Cols VLT_CR SMP PORLEV 1 0 LVDTBEN VM 2 0 RW 00 1 E4h 4 2 Cols VLT_CMP PUMP LVD PPOR R 00 I O...

Page 465: ...ADC_CR0 ADC_CHS 3 0 READY START ONGOING ADC_EN RW 00 1 A9h SADC_CR1 CVTMD 1 0 TIGSEL 1 0 CLKSEL 2 0 ALIGN_EN RW 00 1 AAh SADC_CR2 REFSEL BUFEN VDBEN VDB_CLKS EL FREERUN RW 00 1 ABh SADC_CR3 LALIGN ADC_TRIM0 2 0 RW 04h 1 ACh SADC_CR4 EXTREF 02h LEGEND X The value after power on reset is unknown C Clearable register or bits R Read register or bit s W Write register or bit s Access is bit specific Re...

Page 466: ...ternal oscillator s system clock from 24 MHz to 6 MHz See the Architectural Description on page 81 in the Internal Main Oscillator chapter for more information The IMO is discussed in detail in the Internal Main Oscillator IMO chapter on page 81 25 1 2 Internal Low Speed Oscillator The Internal Low Speed Oscillator ILO is always on unless the device is operating off an external crystal The ILO is ...

Page 467: ...im Register PLL Lock Enable P1 1 P1 0 ILO Trim Register Vdd CLK32K SYSCLK VC3 SYSCLKX2 VC3SEL Clock Doubler 732 EXTCLK P1 4 EXTCLK Input OSC_CR0 7 ILO_TR 7 0 ECO Trim Register ECO_TR 7 0 IMO_TR 7 0 OSC_CR0 6 Vdd OSC_CR2 2 Clock Divider OSC_CR0 2 0 Clock Divider OSC_CR1 7 4 Clock Divider OSC_CR1 3 0 Clock Divider OSC_CR3 7 0 Sleep Clock Divider OSC_CR2 4 OSC_CR0 4 3 26 29 212 215 216 218 219 SYSCLK...

Page 468: ...SoC blocks When the external clock is selected the SYSCLKX2 signal is still available and serves as a doubler for whatever frequency is input on the external clock pin Following the specification for the external clock input ensures that the internal circuitry of the digital PSoC blocks which is clocked by SYSCLKX2 will meet timing require ments However because the doubled clock is generated from ...

Page 469: ...rnal Clock with a CPU Clock Divider of Two or Greater Figure 25 4 Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One CPUCLK IMO Extenal Clock SYSCLK IOW_ EXTCLK bit IMO is deselected External clock is selected CPUCLK IMO External Clock SYSCLK IOW EXTCLK IMO is deselected External clock is selected ...

Page 470: ...T_CLR0 register for the VC3 clock This bit controls the VC3 clock interrupt status Bits 6 to 0 The INT_CLR0 register holds bits that are used by several different resources For a full discussion of the INT_CLR0 register see the INT_CLRx Registers in the Interrupt Controller chapter on page 65 For additional information refer to the INT_CLR0 register on page 199 25 2 2 INT_MSK0 Register The Interru...

Page 471: ...the sleep interrupt signal to GOE 7 This may be useful in real time clock applications where very low power is required By driving the sleep interrupt to a global it may then be routed to a digital PSoC block The digital PSoC block may then count several sleep interrupts before generating its own interrupt which is used to bring the PSoC device out of the sleep state Bit 6 VC3 This bit enables the...

Page 472: ...en the OSC_CR4 1 0 bits are changed Care should be taken to ensure that blocks using the VC3 clock are either disabled when OSC_CR4 1 0 is changed or not sensitive to glitches Unlike the VC1 and VC2 clock dividers the VC3 clock divider is 8 bits wide Therefore there are 256 valid divider values as indicated by Table 25 3 It is important to remember that even though the VC3 divider has four choices...

Page 473: ...set the VC3 clock generates pending interrupts every number of clock periods equal to the VC3 divider register value plus one Therefore if the VC3 divider register s value is 05h divide by 6 an interrupt occurs every six periods of the VC3 s input clock Another example is if the divider value was 00h divide by one an interrupt is generated on every period of the VC3 clock The VC3 mask bit only con...

Page 474: ...uencies generated from a power of two divide circuit which are selected by a 3 bit code At any given time the CPU 8 to 1 clock mux is selecting one of the available frequencies which is resyn chronized to the 24 MHz master clock at the output Regardless of the CPU speed bit s setting if the actual CPU speed is greater than 12 MHz the 24 MHz operating requirements apply An example of this scenario ...

Page 475: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 E1h OSC_CR1 VC1 Divider 3 0 VC2 Divider 3 0 RW 00 Table 25 6 OSC_CR1 7 4 Bits VC1 Divider Value Bits Divider Source Clock Internal Main Oscillator at 24 MHz External Clock 0000b 24 MHz EXTCLK 1 0001b 12 MHz EXTCLK 2 0010b 8 MHz EXTCLK 3 0011b 6 MHz EXTCLK 4 0100b 4 8 MHz EXTCLK 5 0101b 4 MHz EXTCLK 6 0110b 3 43 MHz EXTCLK 7 0111b 3 MHz EXTCLK 8 1000b ...

Page 476: ...e watchdog timer and sleep timer Bit 2 EXTCLKEN When the EXTCLKEN bit is set the external clock becomes the source for the internal clock tree SYSCLK which drives most PSoC device clocking functions All external and internal signals including the 32 kHz clock whether derived from the internal low speed oscillator ILO or the crystal oscillator are synchronized to this clock source If an external cl...

Page 477: ...476 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Digital Clocks ...

Page 478: ... to the Register Details chapter on page 125 26 1 Architectural Description The MAC is a register based system resource Its only interface is the system bus therefore there are no special clocks or enables that are required to be sourced from digital or analog PSoC blocks All CY28xxx devices have two MAC blocks Each MAC is completely independent of the other The architectural presentation of the M...

Page 479: ... multiply accumu late function to take place or a multiply only function The user selects which operation is performed by choosing of input register The multiply function occurs immediately whenever the MULx_X or the MULx_Y multiplier input regis ters are written and the result is available in the MULx_DH and MULx_DL multiplier result registers as discussed in the 26 2 1 Multiplication with No Acc...

Page 480: ...MAC When these write only registers are written the product of the written value and the current value of the MULx_Y registers are calculated For additional information refer to the MULx_Y register on page 172 26 3 3 MULx_DH Register The Multiply Result High Byte Register MULx_DH holds the most significant byte of the 16 bit product Bits 7 to 0 Data 7 0 The product of the multiply operation on the...

Page 481: ...register holds the second of four bytes used to hold the accumulator s value This byte is the most significant of the lower 16 bits of the accumulator s value For additional information refer to the MACx_X ACCx_DR1 register on page 175 26 3 6 MACx_Y ACCx_DR0 Register The Accumulator Data Register 0 MACx_Y ACCx_DR0 is the multiply accumulate Y register and the first byte of the accumulated value Bi...

Page 482: ...r on page 177 26 3 8 MACx_CL1 ACCx_DR2 Register The Accumulator Data Register 2 MACx_CL1 ACCx_DR2 is an accumulator clear register and the third byte of the accumulated value Bits 7 to 0 Data 7 0 This register performs two distinct functions therefore two names are used to refer to the same address When the address is written with any value all 32 bits of the accumulator are reset to zero When thi...

Page 483: ...482 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Multiply Accumulate MAC ...

Page 484: ... block Depending on the operating mode little or no processing is required on the final output This greatly reduces the CPU overhead require ment for analog to digital conversion functionality The major functional units within the type 2 decimator block are shown in Figure 27 1 Figure 27 1 Type 2 Decimator Architecture The type 2 decimator block may be divided into two major functional units A log...

Page 485: ...principle Figure 27 3 Sinc2 Filter Block Diagram H z Transfer function of SincN filter with a decimation rate of M H z 1 M N 1 Z M N 1 1 Z 1 N Sinc2 Transfer Function Equation 1 Mux 3x17 DEC REG 17 bit 17 17 17 17 17 1 17 17 17 Bit Full ADDR A0 A1 Mux Out 8 DB DIFF RESULT 17 17 A0 A1 ACCUMULATION DIFFERENTIATION DCLK Accumulator DIFF REG 0 17 bit DCLK DIFF REG 1 17 bit DCLK 17 Bit Full ADDR 17 Bit...

Page 486: ...ACE_A0 ACE_A1 VC3 SYSCLK DECDx DECCx DECSx Clock Gen ACCx_DECC ACCx_DECS CLK_INx 2 0 GOO 2x GOO 2x 1 To SUPDECx X 3 ACE0_CMPO ROW0LUTOx ROW1LUTOx ROW2LUTOx ACE1_CMPO DATA_INx 2 0 BCx POLx DATA_INx 2 0 ACCx_CMPO ROW3LUTOx VC1 VC2 CLK_INx 2 0 ACE_A0 ACE_A1 VC3 SYSCLK DECDx DECCx DECSx Clock Gen ACCx_DECC ACCx_DECS CLK_INx 2 0 GOO 2x GOO 2x 1 To SUPDECx X 2 ACE0_CMPO ROW0LUTOx ROW1LUTOx ROW2LUTOx ACE...

Page 487: ...f 12 digital block outputs to generate decimation clock DCLK as shown in Figure 27 6 This setting is ignored when the Decimation Rate is set in DECx_CR Figure 27 6 27 1 1 3 Single Incremental Gating Clock Supports Six Analog Compare Outputs The bits of ICLKS 3 0 in DEC_CR0 and DEC_CR1 select 1 out of 16 digital block outputs to form gating signal The gat ing signal as well as 6 incremental gating ...

Page 488: ...CLKS Selection D ICLKS Selection 0000b DB02 FO2 0100b DB00 FO0 1000b DB22 FO10 1100b DB20 FO8 0001b DB12 FO6 0101b DB10 FO4 1001b DB32 FO14 1101b DB30 FO12 0010b DB01 FO1 0110b DB03 FO3 1010b DB21 FO9 1110b DB23 FO11 0011b DB11 FO5 0111b DB13 FO7 1011b DB31 FO13 1111b DB33 FO15 Table 27 6 Decimator Interrupt Mapping Result Condition Map to ACCx interrupt The data input is not from ACE0 or ACE1 and...

Page 489: ... refer to the DECx_DH register on page 169 27 2 2 DECx_DL Register The Decimator Data Low registers DEC0_DL DEC1_DL DEC2_DL and DEC3_DL are dual purpose registers and are used to read the low byte of the decimator s output or clear the decimator Bits 7 to 0 Data Low Byte 7 0 When the registers are read the least significant byte of the 16 bit decimator value is returned Depending on how the decima...

Page 490: ... an output register that may subsequently be read by the CPU This timer period is set to be a function of the DELSIG conversion time and may be selected from up to one of twelve digital blocks depend ing on the PSoC device resources with DCLKS0 in this reg ister and DCLKS3 DCLKS2 and DCLKS1 in the DEC_CR1 register If the Decimation Rate bits are set in DECx_CR this setting is overwritten For addit...

Page 491: ... DEC0_CR0 POL GOOO GOOE DATA_IN 2 0 RW 00 1 95h DEC1_CR0 POL GOOO GOOE DATA_IN 2 0 RW 00 1 99h DEC2_CR0 POL GOOO GOOE DATA_IN 2 0 RW 00 1 9Dh DEC3_CR0 POL GOOO GOOE DATA_IN 2 0 RW 00 Decimator GOO Bus Bit 0 Output to GOO 1 1 Output to GOO 3 2 Output to GOO 5 3 Output to GOO 7 Decimator GOO Bus Bit 0 Output to GOO 0 1 Output to GOO 2 2 Output to GOO 4 3 Output to GOO 6 000b ACCx_CMPO the correspond...

Page 492: ...digital block s primary output is selected as a decimator clock source Note that LOW is selected when DSCLK is greater than 1011b For additional information refer to the DEC_CR5 register on page 270 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 96h DEC_CR4 DEC3_EN CLK_IN3 2 0 DEC2_EN CLK_IN2 2 0 RW 00 000b VC1 001b VC2 010b CLKA4 from analog column 4 011b CLKA5 from analog ...

Page 493: ...ion the following equations are used Single Modulator log2 Decimation Rate 1 1 5 Double Modulator log2 Decimation Rate 1 2 Bit 3 Data Format The Data Format bit can be weighted as signed 2s complement output or unsigned offset binary data Bits 2 to 0 Decimation Rate The devices with type 2 dec imator blocks have the choice of using an internal or exter nal timer If an internal timer is used the us...

Page 494: ... through firmware support Hardware functionality provides basic I2C control data and status primitives A combination of hardware support and firmware command sequencing provides a high degree of flexibility for implementing the required I2C functionality Hardware limitations in regards to I2C are as follows Because receive and transmitted data are not buffered there is no support for automatic rec...

Page 495: ...dware 1 In firmware address comparison mode at the point where eight bits of the address RW byte are received a byte complete interrupt is generated Following the low of the clock the bus is stalled by holding the SCL line low until the PSoC device has a chance to read the address byte and compare it to its own address It will issue an ACK or NAK command based on that compari son 2 In hardware add...

Page 496: ...th a write to the I2C_SCR register Master may transmit another byte or STOP M8C reads the received byte from the I2C_DR register ACK Master wants to read another byte NACK Master says end of data NACK Slave says no more ACK OK to receive more An interrupt always happens in firmware comparison mode and only happens when address matching in hardware comparison mode The SCL line is held low An interr...

Page 497: ...errupt it means that the unit is operating in Slave mode In this case the data register has the master s address data 2 If another master starts a transmission at the same time as this unit arbitration occurs If this unit loses the arbi tration the LostArb status bit is set In this case the block releases the bus and switches to Slave operation When the Start Address interrupt occurs the data regi...

Page 498: ...ress The hardware address automatic compare feature is avail able in slave only mode master slave mode is not sup ported For additional information refer to the I2Cx_ADDR register on page 284 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 Axh I2Cx_ADDR HwAddrEn Addr 6 0 RW 00 LEGEND Xx An x in the address field indicates that there are multiple instances of the register For ...

Page 499: ...er the detection of a bus error will generate an inter rupt A bus error is typically a misplaced Start or Stop This is an important interrupt with respect to Master opera tion When there is a misplaced Start or Stop on the I2C bus all slave devices including this device if Slave mode is enabled will reset the bus interface and synchronize to this signal However when the hardware detects a bus erro...

Page 500: ...lave mode to ensure that there is adequate setup time from data output to the next clock on the release of a slave stall When the Enable Slave and Enable Master bits are both 0 the block is held in reset and all status is cleared See Figure 28 4 for a description of the interaction between the Master Slave Enable bits Block enable will be synchronized to the SYSCLK clock input see Timing Diagrams ...

Page 501: ...lock is idle or a Slave receiver is ready to receive the first bit of a new byte after an ACK Any other timing for a Stop condition causes the Bus Error bit to be set Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 xxh I2Cx_SCR Bus Error Lost Arb Stop Status ACK Address Transmit LRB Byte Complete 00 LEGEND Access is bit specific Refer to Table 28 5 for detailed bit descriptio...

Page 502: ... In Slave mode when this status is set firmware will read the received address from the data register and compare it with its own address If the address does not match the firmware will write a NAK indication to this register No further inter rupts will occur until the next address is received If the address does match firmware must ACK the received byte then Byte Complete interrupts are generated...

Page 503: ... only valid for reading when the Byte Complete status bit is set Data bytes must be read from the register before writing to the I2C_SCR register which continues the transfer Master Start or Restart Address bytes must be written in I2C_DR before the Start or Restart bit is set in the I2C_MSCR register which causes the Start or Restart to generate and the address to shift out Master or Slave Transm...

Page 504: ...s upon whether Slave mode is enabled Slave mode is enabled A Start and address byte interrupt is generated When reading the I2C_MSCR the master will see that the Start Gen bit cleared indicating that the Start was generated However the Lost Arb bit is set in the I2C_SCR reg ister The Address status is also set indicating that the block has been addressed as a slave The firm ware may then ACK or NA...

Page 505: ...ctions When the block is disabled all internal state is held in a reset state When either the Master or Slave Enable bits in the I2C_CFG register are set the reset is synchronously released and the clock generation is enabled Two taps from the ripple divider are selectable 4 16 from the clock rate bits in the I2C_CFG register If any of the two divider taps is selected that clock is resynchronized ...

Page 506: ...lock following a valid SCL positive edge input transition after the synchronizers The Address bit is set with the same timing but only after a slave address has been received The LRB Last Received Bit status is also set with the same timing but only on the ninth bit after a transmitted byte Figure 28 7 Byte Complete Address LRB Timing Figure 28 8 shows the timing for Stop Status This bit is set an...

Page 507: ...nd ing to 16 32 times sampling rates During this initial SCL high period if an external Start is detected the Start sequence is aborted and the block returns to an IDLE state However on the next Stop detection the block will automatically initiate a new Start sequence Figure 28 10 Basic Master Start Timing CLOCK SCL SDA_IN Synchronized BUS ERROR and INTERRUPT SDA START DETECT Misplaced Start Mispl...

Page 508: ...Master Stop Start Chaining SCL SDA CLOCK BUS BUSY SDA_IN Synchronized STOP START DETECT SCL_OUT SDA_OUT OTHER MASTER SDA OTHER MASTER SCL START STOP 8 Clocks 8 Clocks 7 Clocks 4 7 s 6 Clocks 4 0 s Minimum Bus Free Minimum Start Hold SCL SDA CLOCK SDA_IN Synchronized STOP START DETECT SCL_OUT SDA_OUT START STOP 5 13 Clocks 8 16 Clocks 2 Clocks ...

Page 509: ...the following 3 half bit times as shown Figure 28 13 Master Restart Timing 28 5 6 Master Stop Timing Figure 28 14 shows basic Master Stop timing To generate a Stop the SDA line is first pulled low in accordance with the basic SDA output timing Then after the full low of SCL is completed and the SCL line is pulled high the SDA line remains low for a full one half bit time before it is pulled high t...

Page 510: ... Arbitration Timing Figure 28 16 shows a Lost Arbitration sequence When contention is detected at the input SDA_IN sampling point the SDA output is immediately released to an IDLE state However the master continues clocking until the Byte Complete interrupt which is processed in the usual way Any write to the I2C_SCR register results in the master reverting to an IDLE state one clock after the nex...

Page 511: ...e worst case latency for input synchronization of three clocks giving a net period of 8 16 clocks for both high and low time This results in an overall clocking rate of 16 32 clocks per bit In multi master environments when the hardware outputs a 1 on the SCL output if any other master is still asserting a 0 the clock counter will hold until the SCL input line matches the 1 on the SCL output line ...

Page 512: ...e Reference The Internal Voltage Reference is trimmed for gain and temperature coefficient using the BDG_TR register The register description below has an associated register table showing the bit structure The bits that are grayed out in the table are reserved bits and are not detailed in the register description that follows Reserved bits should always be written with a value of 0 29 2 1 BDG_TR ...

Page 513: ...512 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Internal Voltage Reference ...

Page 514: ... code determines that Flash reads are not valid The occurrence of a reset is recorded in the Status and Con trol registers CPU_SCR0 for POR XRES and WDR or in the System Status and Control Register 1 CPU_SCR1 for IRESS Firmware can interrogate these registers to deter mine the cause of a reset 30 2 Pin Behavior During Reset Power on Reset and External Reset cause toggling on two GPIO pins P1 0 and...

Page 515: ...rim value must also be changed when SLIMO is set see Engaging Slow IMO on page 81 When not in external clocking mode the IMO is the source for SYSCLK there fore when the speed of the IMO changes so will SYSCLK Bit 3 ECO EXW The ECO Exists Written bit is used as a status bit to indicate that the ECO EX bit has been previ ously written to It is read only When this bit is a 1 this indi cates that the...

Page 516: ...r XRES Bit 3 Sleep The Sleep bit is used to enter Low Power Sleep mode when set To wake up the system this register bit is cleared asynchronously by any enabled interrupt There are two special features of this register bit that ensures proper Sleep operation First the write to set the register bit is blocked if an interrupt is about to be taken on that instruction boundary immediately after the wr...

Page 517: ...1 the IMO is powered off for low power during start up After XRES deasserts the IMO is started see Figure 30 4 How the XRES configures register reset status bits is shown in Table 30 1 30 4 3 Watchdog Timer Reset The user has the option to enable the Watchdog Timer Reset WDR by clearing the PORS bit in the CPU_SCR0 register When the PORS bit is cleared the watchdog timer cannot be disabled The onl...

Page 518: ...11 N 512 Follows POR XRES IMO PD IMO not to scale CPU Reset PPOR with no IPOR Reset while PPOR is high and to the end of the next 32K cycle IMO off 1 cycle IMO on before the CPU reset is released Note that at the 5V level PPOR will tend to be brief because the reset clears the POR range register VLT_CR back to the default 3V setting CLK32 PPOR Sleep Timer 0 1 2 Reset IPOR PPOR IMO PD IMO not to sc...

Page 519: ...y to refresh the sampled bandgap voltage value This sampling follows the same process used during sleep mode The IMO is always on for at least one CLK32K cycle before CPU reset is deasserted Table 30 1 Details of Functionality for Various Resets Item IPOR Part of POR PPOR Part of POR XRES WDR Reset Length While POR 1 While PPOR 1 plus 30 60 s 1 2 clocks While XRES 1 30 s 1 clock Low Power IMO Off ...

Page 520: ... pump is realized by connecting an external inductor between VBAT and the SMP pin with an external diode pointing from the SMP pin to the Vdd pin A bypass capacitor of at least 0 1 F must be connected between Vdd and Vss The inductor is charged when the internal SMP switch is on When this switch is turned off a Flyback mode occurs and the inductor energy is released into the bypass capacitor This ...

Page 521: ...g components for the SMP For more information refer to the PSoC Application Note 2097 on the web at http www cypress com psoc Inductor The inductor value determines how much load current can be supplied by the SMP Efficiency of the SMP is also affected by the inductor In general a larger inductor provides a higher efficiency The following efficiency and load curves are based on silicon test result...

Page 522: ... The SMP is enabled when the SMP bit is 0 Thus the SMP is on by default If this bit is set to 1 the SMP will not turn on regardless of the supply volt age level Bits 5 and 4 PORLEV 1 0 These bits set the Vdd level at which PPOR switches to one of three valid values Note that 11b is a reserved value and therefore should not be used The three valid settings for these bits are 00b 2 9 V operation 01b...

Page 523: ...522 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Switch Mode Pump SMP ...

Page 524: ...vice Characteristics on page 24 The bits that are grayed out in the register tables are reserved bits and are not detailed in the register descriptions that follow Reserved bits should always be written with a value of 0 For a complete table of the POR and LVD registers refer to the Summary Table of the System Resource Registers on page 462 32 2 1 VLT_CR Register The Voltage Monitor Control Regist...

Page 525: ...fer to the VLT_CR register on page 299 32 2 2 VLT_CMP Register The Voltage Monitor Comparators Register VLT_CMP is used to read the state of internal supply voltage monitors Bit 3 NoWrite This bit is only used in PSoC devices with a 2 4 V minimum POR It reads the state of the Flash write voltage monitor Bit 2 PUMP This bit reads the state of the Switch Mode Pump Vdd comparator The trip points for ...

Page 526: ...t analog columns for simultaneous signal processing 33 1 1 IOMUX and GPIO For each pin the mux capability exists in parallel with the normal GPIO cell described in the General Purpose I O GPIO chapter on page 73 and shown in Figure 33 2 Nor mally the associated GPIO pin is put into a high impedance state for these applications although there are cases where the GPIO cell is configured by the user ...

Page 527: ...d low under firmware control using its pin s GPIO cell After that the capacitor is charged through charge sharing with the sense capacitor The sense capacitor can be automatically initialized and sensed for a number of cycles to build up sufficient charge on the integration capacitor Several clocking choices are available for selection in the AMUX_CFG register The break before make circuitry is co...

Page 528: ... a difference A system with several sense capacitors can be measured in sequence using the same integration capaci tor A pin used as the integration capacitor is not switched dur ing this process so it remains connected to the analog mux Two Port 0 pins are available for this function as shown in Figure 33 4 To activate the charge transfer mode the precharge clock must be set to any state except t...

Page 529: ...rrent In the CY8C28x13 CY8C28x33 CY8C28x45 and CY8C28x52 PSoC devices there is a two channel IDAC 33 4 Register Definitions The following registers are only associated with the Analog Bus Mux in the CY8C28x13 CY8C28x33 CY8C28x43 CY8C28x45 and CY8C28x52 PSoC devices and are listed in address order within their system resource configuration For a complete table of the I O Analog Multiplexer register...

Page 530: ...6 ABusMux2 0 Select analog column 2 input to ana log column 2 mux output Selects among Port 0 pins 1 Select analog column 2 input to the analog mux bus left Bit 5 ACol3Mux 0 Select analog column 3 input to ana log column 3 input mux output 3 Column selects among P0 6 4 2 0 1 Select analog column 3 input to analog column 2 input mux output 2 Column selects among P0 7 5 3 1 Bit 4 ACol0Mux 0 Select a...

Page 531: ...f four phases as listed These settings can be used to optimize noise performance by varying the analog mux sampling point relative to the system clock 00b Synchronize to SYSCLK rising edge 01b Synchronize to delayed approximately 5 ns SYSCLK rising edge 10b Synchronize to SYSCLK falling edge 11b Synchronize to early approximately 5 ns SYSCLK ris ing edge For additional information refer to the AMU...

Page 532: ... or not the left channel IDAC mode is enabled For additional information refer to the IDAC_CR0 register on page 309 33 4 9 IDAC_CR1 Register Bit 7 EN1 This bit controls whether or not the right chan nel IDAC mode is enabled Bit 6 MuxClkGE1 This bit controls connection of the ana log mux bus right clock MUXCLK1 signal to a global Bit 5 ICEN When enabled both left and right IDAC will use IDAC0_D for...

Page 533: ...532 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G I O Analog Multiplexer ...

Page 534: ...in ute counter will increase by 1 for every 60 seconds The hour counter will increase by 1 for every 60 minutes and for every 24 hours there will be an optional day interrupt As shown in Figure 34 1 for Counter65536 VC1 and CLK32K are two optional clock sources When VC1 is selected as the clock input the RTC block can be used as a fixed period timer based on the VC1 period Figure 34 1 BCD counters...

Page 535: ... that follow Reserved bits should always be written with a value of 0 34 2 1 RTC_H This register is used to read and write the current hour value in BCD format Writing to this register will reset count65536 to all zeros Will be displayed as XY the legal range is from 00 to 23 Bits 5 and 4 X value of hour Bits 3 to 0 Y value of hour 34 2 2 RTC_M This register is used to read and write the current m...

Page 536: ... source selection 0 CLK32K 1 VC1 Bits 3 and 2 INT_SEL 1 0 RTC interrupt source selec tion 00b Second 01b Minute 10b Hour 11b Day Bit 1 SYNCRD_EN Sync read enable control 0 Disable sync read 1 Enable sync read Bit 0 RT_EN RTC module enable control 1 Enable RTC module 0 Disable RTC module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 A7h RTC_CR INT_EN CLKSE INT_SEL 1 0 SYNCRD...

Page 537: ...536 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Real Time Clock RTC ...

Page 538: ...e 35 1 SAR ADC Controller Top Level Block Diagram 35 1 1 ADC Clock Generation The ADC clock is the clock to ADC comparator and is derived from SYSCLK It can be SYSCLK 2 4 6 8 12 16 32 or 64 a total of eight selections The ADC clock is targeted to provide a 2 MHz maximum clock to the ADC comparator A spe cial arrangement of 75 25 duty cycle is used because the ADC comparator needs more time to sett...

Page 539: ...tedly until you disable the ADC controller How ever the SW trigger is still available and a new conversion is started if a SW trigger is received The third mode is HW trigger mode also called auto trigger mode or auto align mode Select one of four hardware trigger sources and use it to trigger START It acts similarly to SW trigger mode but the trigger source is changed 35 1 4 SAR Algorithm and Dat...

Page 540: ... the following figures Figure 35 4 A D C Operation Mode 0 Default Mode Figure 35 5 A D C Operation Mode 1 Figure 35 6 A D C Operation Mode 2 Figure 35 7 A D C Operation Mode 3 1 2 3 4 5 6 7 8 9 10 11 12 13 ADC_CLK S_H SOLSB 1 WEAKREF 0 3FFF 03FF D 13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 ADC_CLK S_H SOLSB WEAKREF 1 3FFF 03FF D 13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 ADC_CLK S_H SOLSB WEAKREF 1 3FFF 03FF D 13...

Page 541: ... justified mode SADC_DH should be read first then SADC_DL follows The register containing the most useful bits should be read first 35 2 Application Description 35 2 1 ADC Sample Rate and Clock Selection The ADC sample rates are maximum 142 ksps and mini mum 26 7 ksps based on Table 35 3 35 2 2 Voltage Doubler Enable Enable the voltage doubler when Vcc is less than 3 0 V Note that this voltage dou...

Page 542: ...significant 2 bits of the 10 bit sample For additional information refer to the SADC_DL register on page 154 35 3 3 SADC_TSCR0 SADC_TSCR0 selects the source for an external trigger and enables trigger sources Bits 7 to 4 TS_INCMP_SEL 3 0 These bits are used to select external or internal trigger source 0000b GIE 0 0001b GIE 1 0010b GIE 2 0011b GIE 3 0100b GIE 4 0101b GIE 5 0110b GIE 6 0111b GIE 7 ...

Page 543: ...ADC_TSCMPH can be used to form a 16 bit conversion For additional information refer to the SADC_TSCR1 regis ter on page 248 35 3 5 SADC_TSCMPL This register is used to set the compare value of low chan nel Bits 7 to 0 TS_CMPL 7 0 The compare value of low channel For additional information refer to the SADC_TSCMPL reg ister on page 259 35 3 6 SADC_TSCMPH This register is used to set the compare val...

Page 544: ... Vref buffer Refer to Figure 35 5 on page 539 10b the extra cycle for seventh bit conversion with add on weak Vref buffer Refer to Figure 35 6 on page 539 11b the extra cycle for first bit conversion with add on weak Vref buffer Refer to Figure 35 7 on page 539 Bits 5 and 4 TIGSEL 1 0 Auto trigger source selection It must work with ALIGN_EN Refer to bit 0 of this register and SADC_TSCRx 1 71h and ...

Page 545: ...evices Bit 7 LALIGN 1 to left justified data format Bits 2 to 0 ADC_TRIM0 2 0 Sent to ADC comparator block directly The reset value is 100b For additional information refer to the SADC_CR3 register on page 282 35 3 11 SADC_CR4 10 bit SAR ADC controller only exists in the CY8C28x03 CY8C28x13 CY8C28x33 CY8C28x43 and CY8C28x45 PSoC devices Bit 7 EXTREF 1 to select external Vref input on P2 5 For addi...

Page 546: ...gic address The label or number identifying the memory location RAM ROM or register where a unit of information is stored algorithm A procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation ambient temperature The temperature of the air in a designated area particularly the area surrounding the PSoC device analog See analog signal...

Page 547: ...ly irrespective of any clock sig nal attenuation The decrease in intensity of a signal as a result of absorption of energy and of scattering out of the path to the detector but not including the reduction due to geometric spreading Attenuation is usually expressed in dB B bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative t...

Page 548: ...ten use for example A B for OR and for AND for example A B because in some ways those oper ations are analogous to addition and multiplication in other algebraic structures and represent NOT by a line drawn above the expression being negated for example A A_ A break before make The elements involved go through a disconnected state entering break before the new con nected state make broadcast net A...

Page 549: ...gh level language such as C into machine language configuration In a computer system an arrangement of functional units according to their nature number and chief characteristics Configuration pertains to hardware software firmware and documenta tion The configuration will affect system performance configuration space In PSoC devices the register space accessed when the XIO bit in the CPU_F regist...

Page 550: ... serial transmitter CRC generator pseudo random number generator or SPI digital logic A methodology for dealing with expressions containing two state variables that describe the behavior of a circuit or system digital to analog DAC A device that changes a digital signal to an analog signal of corresponding magnitude The ana log to digital ADC converter performs the reverse operation direct access ...

Page 551: ...lication of the corresponding signal frequency The number of cycles or events per unit of time for a periodic function G gain The ratio of output current voltage or power to input current voltage or power respectively Gain is usually expressed in dB gate 1 A device having one output channel and one or more input channels such that the output channel state is completely determined by the input chan...

Page 552: ... both running at 5 V and pulled high with resistors The bus operates at 100 kbps in standard mode and 400 kbps in fast mode I2C is a trademark of NXP ICE The in circuit emulator that allows users to test the project in a hardware environment while viewing the debugging device activity in a software environment PSoC Designer idle state A condition that exists whenever user messages are not being tr...

Page 553: ...igit or bit in a binary number that represents the least significant value typically the right hand bit The bit versus byte distinction is made by using a lower case b for bit in LSb least significant byte LSB The byte in a multi byte word that represents the least significant values typically the right hand byte The byte versus bit distinction is made by using an upper case B for byte in LSB Line...

Page 554: ...ucts In addition to a CPU a microcontroller typically includes memory timing circuits and I O circuitry The rea son for this is to permit the realization of a controller with a minimal quantity of chips thus achieving maximal possible miniaturization This in turn will reduce the volume and the cost of the controller The microcontroller is normally not used for general purpose computation as is a m...

Page 555: ...O OR See Boolean Algebra oscillator A circuit that may be crystal controlled and is used to generate a clock frequency output The electrical signal or signals which are produced by an analog or digital block P parallel The means of communication in which digital data is sent multiple bits at a time with each simul taneous bit being sent over a separate line parameter Characteristics for a given bl...

Page 556: ...This is one type of hardware reset program counter The instruction pointer also called the program counter is a register in a computer processor that indicates where in memory the CPU is executing instructions Depending on the details of the particular machine it holds either the address of the instruction being executed or the address of the next instruction to be executed protocol A set of rules...

Page 557: ...n analog signal into a series of digital values or reversed schematic A diagram drawing or sketch that details the elements of a system such as the elements of an electrical circuit or the elements of a logic diagram for a computer seed value An initial value loaded into a linear feedback shift register or random number generator serial 1 Pertaining to a process in which all events occur one after...

Page 558: ...device SROM An acronym for supervisory read only memory The SROM holds code that is used to boot the device calibrate circuitry and perform Flash operations The functions of the SROM may be accessed in normal user code operating from Flash stack A stack is a data structure that works on the principle of Last In First Out LIFO This means that the last item put on the stack is the first item that ca...

Page 559: ...igh impedance The function does not drive any value in the Z state and in many respects may be considered to be disconnected from the rest of the circuit allowing another output to drive the same net U UART A UART or universal asynchronous receiver transmitter translates between parallel bits of data and serial bits user The person using the PSoC device and reading this manual user modules Pre bui...

Page 560: ...No 001 52594 Rev G 559 W watchdog timer A timer that must be serviced periodically If it is not serviced the CPU will reset after a specified period of time waveform The representation of a signal as a plot of amplitude versus time X XOR See Boolean Algebra ...

Page 561: ...560 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...

Page 562: ...egister 249 ACE_CLK_CR1 register 459 ACE_CMP_GI_EN register 455 ACExxCR1 register 256 456 ACExxCR2 register 257 457 ACIx bits 145 250 ACK bit 195 ACMux bits 162 AColxMux bits 80 238 255 acronyms 28 ADC Clock Generation 10 bit SAR ADC controller 537 ADC FSM 10 bit SAR ADC controller 538 A D C Operation Mode 10 bit SAR ADC controller 539 ADC Sample Rate 10 bit SAR ADC controller 540 ADC_CR0 register...

Page 563: ...hardware acceleration 396 synchronization interface 396 analog modulator interface 396 in two column limited analog system 444 analog mux bus 526 analog output drivers 79 architecture 79 configurations 79 register definitions 80 analog reference 421 analog ground bypass 422 architecture 421 in two column limited analog system 450 register definitions 422 analog single slope ADC in two column limit...

Page 564: ...lock external digital clock 467 clock doubler 467 switch operation 467 clocking in SROM 55 rates for I2C 499 ClockPhase bit in ASCxxCR0 register 161 in ASDxxCR0 register 165 clocks digital See digital clocks CMOUT bit 156 CMP_CR0 register 149 251 401 for two column limited analog system 455 CMP_CR1 register 151 252 403 for two column limited analog system 455 CMP_GO_EN register 240 406 CMP_GO_EN1 ...

Page 565: ... 339 kill options 340 register definitions 350 timing 367 DEC_CR0 register 212 403 453 489 DEC_CR1 register 213 267 268 270 404 453 489 DEC_CR4 register 269 decimator 483 architecture 483 configurations 483 register definitions 488 type 2 block 483 decimator and incremental ADC interface 395 DECx_CR register 290 492 DECx_DH register 170 488 DECx_DL register 169 488 DECxCR0 register 267 490 destina...

Page 566: ...NT bit 70 206 EraseAll function in SROM 53 EraseBlock function in SROM 52 erasing a block in Flash 52 user data in Flash 53 EXGAIN bit 156 EXTCLKEN bit 95 298 external crystal oscillator 87 architecture 87 external components 88 register definitions 89 external digital clock 467 external reset 516 F FCap bit in ASCxxCR0 register 161 in ASDxxCR0 register 165 Flash checksum 53 clocking strategy 55 e...

Page 567: ...03 307 IMO See internal main oscillator incremental ADC interface 395 index memory page pointer in RAM paging 59 input for digital blocks clock resynchronization 336 multiplexers 336 INSAMP bit 156 instruction amplifiers 427 instruction formats 1 byte instructions 42 2 byte instructions 42 3 byte instructions 43 instruction set summary 40 41 INT_CLR0 register 68 199 469 INT_CLR1 register 68 201 IN...

Page 568: ... register 159 in ACExxCR1 register 256 NMux connections 410 in two column limited analog system 445 No Buzz bit 94 296 numeric naming conventions 27 O On Chip Debug OCD parts 34 Ongoing bit 10 bit SAR ADC controller 540 OSC_CR0 register 90 94 102 296 473 OSC_CR1 register 297 474 OSC_CR2 register 82 91 95 103 298 475 OSC_CR3 register 295 472 OSC_CR4 register 294 471 OSC_GO_EN register 293 470 OSCMD...

Page 569: ... time clock 533 architecture 533 BCD Code Counter 533 General Timer 534 reading RTC data 533 register definitions 534 writing RTC data 533 receiver for digital blocks functionality 345 register definitions 353 timing 379 REF bits 148 register conventions 27 126 register definitions 10 bit SAR ADC controller 541 analog input configuration 419 analog interface 400 analog output drivers 80 analog ref...

Page 570: ...216 SLP_EXTEND bit 298 SMP See switch mode pump source instructions direct 44 immediate 43 indexed 44 indirect post increment 47 SPI Complete bit 140 141 SPI for digital blocks master function 344 master register 352 mode timing 370 protocol function 343 slave function 344 slave register 352 SPIM timing for digital blocks 371 SPIS timing for digital blocks 374 SplitMux bit 309 SROM See supervisory...

Page 571: ... limited analog system 441 analog array 445 analog comparator bus interface 442 analog input configuration 446 analog interface 441 analog reference 450 architecture 441 column clock generation 442 continuous time block 450 device distinctions 450 LUT function 442 modulator interface 444 NMux connections 445 PMux connections 446 PWM ADC interface 444 register definitions 452 sample and hold featur...

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