CMT2380F64
www. cmostek. com
Rev 0.3 | 51 / 83
The PJD technique is similar to the traditional carrier sense technique, but more reliable. While users combine the RSSI
detection and PJD technique, they can precisely identify the status of the current channel.
4.9 Clock Data Recovery
（
CDR
）
The basic task of a CDR system is to recover the clock signal that is synchronized with the symbol rate, while receiving the data.
Not only for decoding inside the chip, but also for outputting the synchronized clock to GPIO for users to sample the data. So
CDR's task is simple and important. If the recovered clock frequency is in error with the actual symbol rate, it will cause data
acquisition errors at the time of reception.
CMT2380F64 has designed three types of CDR systems, as followed:
⚫
COUNTING system
– The system is designed for the symbol rates to be more accurate. If the symbol rate is100%
aligned, the unlimited length of 0 can be received continuously without error.
⚫
TRACING system
– The system is designed to correct the symbol rate error. It has the tracking function. It can
automatically detect the symbol rate transmitted byTX, and adjust quickly the local symbol rate of RX at the sametime,
so as to minimize the error between them. The system can withstand up to 15.6% symbol rate error. Other similar
products in the industry cannot reach this level.
⚫
MANCHESTER system
–This system evolves from the COUNTING system. The basic feature is the same. The only
difference is that the system is specially designed for Manchester codec. Special processing can be done when the TX
symbol rate has unexpected changes
4.10
Fast Frequncy Hopping
The mechanism of fast frequency hopping is, based on the frequency configured on the RFPDFK, for instance 433.92 MHz, during
applications the MCU can simply change 1 or 2 registers to quickly switch to another frequency points. This simplify theway of change
the RX or TX frequency in multiple channels application.
𝐅𝐑𝐄𝐐 = 𝐁𝐚𝐬𝐞 𝐅𝐫𝐞𝐪 + 𝟐. 𝟓 𝐤𝐇𝐳 × 𝐅𝐇_𝐎𝐅𝐅𝐒𝐄𝐓 < 𝟕: 𝟎 >× 𝐅𝐇_𝐂𝐇𝐀𝐍𝐍𝐄𝐋 < 𝟕: 𝟎 >
In general, users can configure FH_OFFSET<7:0>during the chip initialization process. And then in the application, users
can switch the channel by changing FH_CHANNEL<7:0>.
When users need to use the fast frequency hopping in the RX mode, in some particular frequency points, one parameter of theAFC
circuit must be re-configured. Please refer to
AN197-CMT2300A-CMT2119B-CMT2219B fast frequency hopping
and
CMT2300A-CMT2219B frequency hopping calculation tool
for more details.
4.11 Chip Operation
4.11.1
SPI Interface
The chip communicates with the outside through the 4-wire SPI interface (FCSB
、
CSB
、
SDA
、
SCLK).The CSB is the active-low
chip select signal for accessing to the registers. The FCSB is the active-low select signal for accessing to the FIFO.They cannot
be set to low at the same time. The SCLK is the serial clock. Its highest speed is 5MHz.The chip itself and the external MCU
send the data at the falling edge of SCLK and capture the data at the rising edge of SCLK. The SDIO is a bidirectional pin for
input and output data. The address and data are transferred starting from the MSB.
When accessing to the register, CSB is pulled low. A R/W bit is sent first, followed by a 7-bit register address. After the external
MCU pulls down the CSB, it must wait for at least half a SCLK cycle, and then send the R/W bit. After the MCU sends out the last
falling edge of SCLK, it must wait for at least half a SCLK cycle, and then pull the CSB high.
