CMT2380F64
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Rev 0.3 | 26 / 83
1.
The measuring point is set at CMOS level: 0.3 VDD and 0.7 VDD.
1.21 SPI/I2S Characteristic
For feature details of the input and output multiplexing pins (WS, CLK, SD of NSS, SCLK, SPI, MOSI, MISO, I2S, ),
see Section 1.17.
SPI
C
haracteristics
(4)
Symbol
Parameter
Conditions
Min
Max
Unit
f
SCLK
1/t
c(SCLK)
SPI clock frequency
Master mode
-
18
MHz
Slave mode
-
18
t
r(SCLK)
t
f(SCLK)
SPI clock rise and fall time
Load capacitance: C = 30 pF
-
8
ns
DuCy(SCK)
SPI slave input clock duty
cycle
SPI Slave mode
30
70
%
t
su(NSS)
(1)
NSS establishment time
Slave mode
4t
PCLK
-
ns
t
h(NSS)
(1)
NSS retention time
Slave mode
2t
PCLK
-
ns
t
w(SCLKH)
(1)
t
w(SCLKL)
(1)
SCLK high and low time
Master mode
PCLK
t
PCLK
+ 2
ns
t
su(MI )
(1)
Data input setup time
Master mode
SPI 1
19.84
-
ns
SPI 2
20.5
-
t
su(SI)
(1)
Slave mode
SPI 1
4.16
-
SPI 2
4.16
-
t
h(MI)
(1)
Data input retention time
Master mode
0
-
ns
t
h(SI)
(1)
Slave mode
4
-
t
a(SO)
(1)(2)
Data output access time
Slave mode
，
f
PCLK
= 20 MHz
0
3t
PCLK
ns
t
dis(SO)
(1)(3)
Disabled time for data
output
Slave mode
2
10
ns
t
v(SO)
(1)
Valid time of data output
Slave mode
(after the enabled edge)
SPI 1
-
32
ns
SPI 2
-
30
t
v(MO)
(1)
Mastermode
(after theenabled edge)
SPI 1
-
28
SPI 2
-
28
t
h(SO)
(1)
Data output retention time
Slave mode
(after the enabled edge)
0
-
ns
t
h(MO)
(1)
Master mode
(after the enabled edge)
0
-
1. Guaranteed by design and comprehensive evaluation, not tested in production.
2. The minimum value means the minimum time to drive the output, and the maximum value means the maximum time to get the
data correctly.
3. The minimum value means the minimum time to turn off the output, and the maximum value means the maximum time to put the
data line in the high resistance state.
4. Test voltage is 3.3 V.
t
