CMT2380F64
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Rev 0.3 | 17 / 83
DuCy
(HSE)
Duty cycle
(1)
45
-
55
%
I
L
OSC_IN
input leakage current
(1)
VSS≤VIN≤VDD
-
-
±1
μA
•
1.
Guaranteed by design and comprehensive evaluation, not tested in production.
90%
10%
V
HSEH
V
HSEL
t
r(HSE)
t
f(HSE)
T
HSE
t
W(HSE)
t
W(HSE)
t
External clock
source
OSC_IN
f
HSE_ext
The AC timing diagram of the external high-speed clock source
⚫
Low-speed external user clock generated from external oscillation sources
Low-speed external user clock features
Symbol
Parameter
Condition
Min
Typ
Max
Unit
f
LSE_ext
User external clock frequency
-
0
32.768
1000
KHz
V
LSEH
OSC32_IN input pin at high-level
voltage
(1)
0.7 V
DD
-
V
DD
V
V
LSEL
OSC32_IN input pin at low-level
voltage
(1)
V
SS
-
0.3 V
DD
tw
(LSE)
OSC32_IN high /low time
(1)
450
-
-
ns
t
r(LSE)
t
f(LSE)
OSC32_IN up/ down time
(1)
-
-
10
DuCy
(LSE)
Duty cycle
(1)
30
-
70
%
I
L
OSC32_IN input leakage current
(1)
V
SS
≤V
IN
≤V
DD
-
-
±1
μA
1. Guaranteed by design and comprehensive assessment, not tested in production
。
