CMT2380F64
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Rev 0.3 | 25 / 83
I2C Characteristics
Symbol
Parameter
Standard model
Fast mode
Fast + mode
Unit
Min
Max
Min
Max
Min
Max
SCL
I2C interface frequency
0
100
0
400
0
1000
KHz
th
(STA)
Start condition holding time (1)
4.0
-
0.6
-
0.26
-
μs
t
w(SCLL)
SCL Clock Low Time (1)
4.7
-
1.3
-
0.5
-
μs
t
w(SCLH)
SCL clock high time (1)
4.0
-
0.6
-
0.26
-
μs
t
su(STA)
Establishment time of repeated starting
conditions (1)
4.7
-
0.6
-
0.26
-
μs
t
h(SDA)
SDA data retention
time (1)
-
3.4
-
0.9
-
0.4
μs
t
su(SDA)
Establishment time of SDA (1)
250
-
100
-
50
-
ns
t
r(SDA)
t
r(SCL)
SDA and SCL rise time (1)
-
1000
20+0.
1Cb
300
-
120
ns
t
f(SDA)
t
f(SCL)
SDA and SCL fall
time (1)
-
300
20+0.
1Cb
300
-
120
ns
t
su(STO)
Establishment time of stop condition(1)
4.0
-
0.6
-
0.26
-
μs
t
w(STO:STA)
Time from stop condition to start condition
(bus idle) (1)
4.7
-
1.3
-
0.5
-
μs
Cb
Capacity load per bus (1)
-
400
-
400
-
200
pf
t
v(SDA)
Data validity time(1)
3.45
-
0.9
-
0.45
-
μs
t
v(ACK)
Response validity time (1)
3.45
-
0.9
-
0.45
-
μs
1. Guaranteed by design and comprehensive evaluation, not tested in production.
2.
To achieve the maximum frequency of standard mode I2C, FPCLK1 must be greater than 2 MHz.To achieve the maximum frequency
of fast mode I2C, FPCLK1 must behigher than 4 MHz.
SDA
SCL
100
100
VDD VDD
I2C
总线
t
su(STA)
t
w(STA STO)
Stop
condition
开始条件
Repetitive
startup
condition
Startup
condition
SDA
SCL
t
f(SDA)
t
r(SDA)
t
w(SCLL)
t
w(SCLH)
t
r(SCL)
1/f
SCL
1
st
clock
t
f(SCL)
t
su(STO)
t
v(ACK)
9
th
Clock
t
v(SDA)
t
su(SDA)
t
h(SDA)
I
2
C Bus AC waveform and measurment circuit
(1)
f
