CMT2380F64
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◼
VDDA area
：
The voltage input range is 1.8 V~3.6 V
，
which supplies power for most of the external analog
peripherals. For more information, please refer to the electrical characteristics section of the relevant data
manual.
◼
VDDD area
：
The voltage regulator supplies power for CPU, AHB, APB, SRAM, FLASH and most of the digital
peripheral interfaces.
◼
PWR is the power control module of the entire device, its main function is to control CMT2380F64 to enter
different power modes and can be awakened by other events or interrupts. CMT2380F64 supports RUN,
LPRUN, SLEEP, STOP and PD modes.
5.6
Programmable voltage monitor
The power-on reset (POR) and power-down reset (PDR) circuits are integrated internally. This part of the circuit is always in
working condition to ensure that the system works normally when the power supply voltage exceeds 1.8 V. When VDD is lower
than the set threshold (VPOR/PDR), the device remains in the reset state. The device has a programmable voltage monitor (PVD),
which monitors the MCU_VDD/ MCU_VDDA power supply and compares it with the threshold VPVD. When VDD is lower or
higher than the threshold VPVD, it will generate an interrupt. The PVD function is turned on by software.
For the values of VPOR/PDR and VPVD, please refer to the table for Embedded Reset and Power Control Module Features
5.7 Low Power Mode
CMT2380F64 is in operation mode after system reset or power-on reset. When the CPU does not need to run(for
example, waiting for external events
）
, users can choose to enter a low-power mode to save power.
CMT2380F64 has the following four low-power modes
：
◼
LPRUN mode
（
low-power operation mode
，
the system is in 32.768 KHz low-frequency operation mode
）
◼
SLEEP mode
（
the core is stopped, all peripherals including Cortex®-M0 core peripherals (such as NVIC, SysTick are
still running
）
◼
STOP mode
（
most of the clocks are turned off, the voltage regulator is still running in low power consumption mode
）
◼
PD mode
（
VDDD power-down mode
，
VDD hold
，
3 WAKEUP IO and NRST can be wake up
）
◼
In addition
，
the following methods can also reduce the power consumption in RUN mode:
⚫
Reduce the system clock frequency
⚫
Turn off the unused peripheral clocks on the APB and AHB buses
⚫
Optional configuration of PWR_CTRL4.STBFLH in RUN mode allows FLASH to enter deep standby mode; when
exiting, the system needs to wait about 10 us before re-accessing FLASH
5.8 Direct Memory Access
（
DMA
）
Integrated 1 general purpose 5-channel DMA controller to manage memory-to-memory, peripheral-to-memory, and
memory-to-peripheral data transfer; Each channel has a dedicated hardware DMA request logic, and each channel can be
triggered by the software. The transmission length of each channel, source address and destination address of transmission can
be set separately by software.
DMA can be used for the main peripherals: SPI, I2C, USART, Universal, Basic and Advanced Control Timers TIMx, I2S, ADC.
5.9 Real Time Clock
（
RTC
）
Real Time Clock (RTC) has a set of BCD timers/counters that count independently and continuously. Under the
corresponding software configuration, it can provide calendar function. The RTC can also provides two programmable clock
interrupts.
Two 32-bit registers contain decimal format (BCD) for subseconds, seconds, minutes, hours (in 12 or 24 hour format), days
of the week, days (date), months, and years.
Subsecond values are provided in binary format as separate 32-bit registers. Additional 32-bit registers
containprogrammable seconds, minutes, hours, days of the week, days, months, and years.
