CMT2380F64
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Rev 0.3 | 49 / 83
Figure 4-1. POR Reset Causing from Sudden Decreasing
The second case is,a slow decrease of the VDD. The POR triggering conditionis, RF-VDD decreases to 1.45 V+/-20% (e.g.1.16
V
–1.74 V) within no less than 2us. To be noticed, it detects absolute value of RF-VDD rather than decreasing amplitude. This
situation is shown as below:
VDD
1.45 V x (1 +/- 20%)
POR
> 0.2 us
Figure 4-2. POR Reset Causing from Slow Decreasing
4.4 Crystal Oscillator
The crystal oscillator provides a reference clock for the phase locked loop as well as a system clock for the digital circuits. The
value of load capacitance depends on the crystal specified CL parameters. The total load capacitance between XI and XO should
be equal to CLto make the crystal accurately oscillate at 26 MHz.
𝐂
𝐋
=
𝟏
𝟏 𝐂𝟏𝟓 + 𝟏 𝐂𝟏𝟔
⁄
⁄
+ 𝐂
𝐩𝐚𝐫
+ 𝟐. 𝟓𝐩𝐅
C15 and C16 are the load capacitances at both ends of the crystal. Cpar is the parasitic capacitance on the PCB. Each crystal pin
has 5pF internal parasitic capacitance, together is equivalent to 2.5pF. The equivalent series resistance of the crystal must be
within the specifications so that the crystal can have a reliable vibration. Also, an external signal source can be connected to the
XI pin to replace the conventional crystal. The recommended peak value of this clock signal is from 300mV to 700mV. The clock is
coupled to XI pin via a blocking capacitor.
4.5 Low power frequency oscillator (LPOSC)
The CMT2380F64 rf system integrates a sleep timer driven by a 32 kHz low power oscillator (LPOSC). When this function is
enabled, the timer periodically wakes the chip from sleep. When the chip is operating in periodic operation mode, the sleep time
can be configured from 0.03125 ms to 41,922,560 ms Since the frequency of the low power oscillator will drift with temperatur e
and voltage changes, it will be automatically calibrated during the power-up phase and will be periodically calibrated. These
calibration will keep the frequency tolerance of the oscillator within 1%
4.6 Internal Low Power Detection
The chip sets up low voltage detection. When the chip is tuned to a certain frequency, the test is performed once. Frequency
tuning occurs when the chip jumps from the SLEEP/STBY state to the RFS/TFS/TX/RX state. The result can be read by the
LBD_VALUE register.
4.7 Received Signal Strength Indicator (RSSI)
RSSI is used to evaluate the signal strength inside the channel. The cascaded I/Q logarithmic amplifier amplifies the signal before
it is sent to the demodulator. The logarithmic amplifier of I channels and Q channel contains the received signal indicator, in which
the DC voltage is generated is proportional to the input signal strength. The output of RSSI is the sum of the values of the two
channels’ signals. The output has 80 dB dynamic range above the sensitivity. After the RSSI output is sampled by the ADC and
filtered by a SAR filter and an average filter. The order of the average filter can be set by RSSI_AVG_MODE<2:0>. The code value
