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◆
The master clock can be output to external audio devices, fixed frequency is 256xFs (Fs is the audio sampling
frequency)
5.15 General purpose input/output
（
GPIO
）
GPIO (General Purpose Input/Output) stands for Generic I/O, AFIO (Alternate-Function Input/Output) stands for Multiplexed
Function I/O.The chip supports up to 23 GPIOs and is divided into 3 groups (GPIOA/GPIOB/GPIOC), group A has 13 ports per
group, group B has 7 ports(among which 4 of them are SPI multiplexing to RF) and group C has 3 ports.GPIO ports share pins with
other reusable peripherals, and users can configure them flexibly according to their needs.Each GPIO pin can be independently
configured as an output, input, or multiplexed peripheral function port.Except for analog input pins, all other GPIO pins have high
current flow capability.
The main characteristics of GPIO are described as follows:
◆
GPIO ports can be configured separately by the software in the following modes:
⚫
Input floated
⚫
Input pull-up
⚫
Input pull down
⚫
Analog function
⚫
Open drain output and up/down can be configured
⚫
Push-pull output and up/down configurable
⚫
Push-pull multiplexing function and up/down configurable
⚫
Open drain multiplexing function and up/down configurable
◆
Separate bit setting or bit clearing
◆
All IO support external interrupt functionality
◆
All IO support low-power mode wake-up, with rising or falling edges configurable
◆
Sixteen EXITs can be used for SLEEP or STOP mode wake up, and all I/O can be reused as EXTI
◆
PA 0/ PC 13/ PA 2 three wake-up IO can be used for PD mode wake-up, I/O filtering time is 1us maximum
◆
Supports software remapping the I/O reusing function
◆
Support GPIO locking mechanism, reset mode to clear the locked state
◆
Each I/O port bit can be programmed arbitrarily, but the I/O port register must be accessed as a 32-bit word
(16-bit half-word or 8-bit byte access is not allowed).
5.16
Analog to digital converter
（
ADC
）
12-bit ADC is a high-speed successive approximation analog-to-digital converter. It has up to 6 channels and can measure 6
external and 3 internal signal sources. The A/D conversion of each channel can be executed in single, continuous, scanning or
discontinuous mode. The ADC result can be left-aligned or right-aligned stored in the 16-bitdata register; ADC input clock must not
exceed 18 MHz.
The main characteristics of ADC are described as follows:
◆
Support 1 ADC, single-ended input, can measure 12 external and 4 internal signal sources
◆
Support 12-bit resolution, the highest sampling rate is 1 MSPS
◆
ADC clock source is divided into working clock source, sampling clock source and timing clock source
⚫
Only AHB_CLK can be configured as a working clock source, up to 48 MHz
⚫
PLL can be configured as a sampling clock source, up to 18 MHz, supportfrequency division 1, 2, 4, 6, 8, 10,
12, 16, 32, 64, 128, 256
⚫
AHB_CLK can be configured as the sampling clock source, up to 18 MHz, support frequency division 1, 2,
4, 6, 8, 10, 12, 16, 32
⚫
The timing clock is used for internal timing functions, and the frequency must be configured to 1 MHz.
◆
Support timer trigger ADC sampling
◆
Interrupts are generated at the end of conversion, the end of injection conversion, and the occurrence of analog
watchdog events
◆
Single and continuous conversion mode
◆
Auto scan mode from channel 0 to channel N
◆
Data alignment with embedded data consistency
◆
Sampling interval can be programmed separately per channel
