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interface can also work in a multi-master configuration.It can be used for a variety of purposes, including dual wire simplex
synchronous transmission using a two-way data line, and reliable communication using CRC calibration.

The main functions of the SPI interface are as follows:

◆

Full-duplex synchronous transmission

◆

Double wire simplex synchronous transmission with or without a third two -way data line

◆

8 or 16 bit transmission frame format selection

◆

Support master mode or slave mode

◆

Support multi-master mode

◆

Fast communication between master mode and slave mode

◆

NSS can be managed by software or hardware in both master mode and slave mode: dynamic

change of master/slave operation mode

◆

Programmable clock polarity and phase

；

◆

Programmable data order, MSB before or LSB before

；

◆

Dedicated send and receive flags th at trigger interrupts

；

◆

SPI bus busy status flag

；

◆

Hardware CRC to support reliable communication:

In send mode, the CRC value can be sent as the last byte

；

In full duplex mode, CRC check is automatically carried out on the last byte received

；

◆

Main mode failures, overloads, and CRC error flags that trigger interrupts

◆

Single-byte send and receive buffers that support DMA functionality: Generates send and receive

requests

◆

Maximum interface speed: 18Mbps

5.14 Synchronous Serial Interchip Sound

（

I2S

）

I2S is a 4-pin synchronous serial interface communication protocol that can operate in master or slave mode. It can
be configured for 16-bit, 24-bit, or 32-bit transmission, as well as input or output channels, and supports audio
sampling frequencies from 8 kHz to 96 kHz. It supports four audio standards, including the Philips I2S standard, the
MSB and LSB alignment standard, and the PCM standard.

It can work in both master and slave modes in half duplex communication. When it is the master device, it provides a clock signal to
an external slave device through the interface.

The main functions of I2S interface are as follows:

◆

Half-duplex communication (only send or receive at the same time);

◆

Master or slave operation;

◆

8-bit linear programmable pre-divider for accurate audio sampling frequency (8kHz to 96kHz);

◆

The data format can be 16-bit, 24-bit, or 32-bit;

◆

Audio channel fixed packet frame is 16 bit (16 bit data frame) or 32 bit (16, 24 or 32 bit data frame);

◆

Programmable clock polarity (stable state);

◆

Overflow flag bits in send mode and overflow flag bits in master/slave receive mode;

◆

16-bit data registers are used for sending and receiving, with one register at each end of the channel;

◆

Supported I2S protocols:

◆

I2S Philips standard

◆

MSB alignment standard (left alignment)

◆

LSB alignment standard (right alignment)

◆

PCM standard (16-bit channel frames with long or short frame synchronization or 16-bit data framesextended to
32-bit channel frames)

◆

Data direction is always MSB first;

◆

Both sending and receiving have DMA capability

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Summary of Contents for CMT2380F64

Page 1: ...lock output which can be configured as configurable system clock HSE HSI or PLL post divided output Reset Supports power on power down external pin reset Supports programmable low voltage detection an...

Page 2: ...and 128 bit UCID RF Features Working frequency 127 1020 MHz Modulation style G FSK G MSK OOK Data rate 0 5 300 kbps Sensitivity 121 dBm 434 MHz FSK RX current 8 5 mA 434 MHz FSK TX current 72 mA 20 d...

Page 3: ...quency hopping and 12 bit high speed ADCmulti channel input etc CMT2380F64 has a small QFN package size of 5mmx5mm 6mmx6mm which is ideal for small size and power consumption of Internet applications...

Page 4: ...C11 C12 C13 C14 C15 C16 R1 Figure1 CMT2380F64 QFN 40 5x5 Typical application diagram 20 dBm power output NC RFIP RFIN RFO RF_AVDD RF_DGND RF_DVDD GPIO3 PC13 PC14 PF0 NRST MCU_VSS MCU_VDD MCU_VDDA PA0...

Page 5: ...1 uF C15 20 0603X7R 25 V 1 uF C16 20 0402 X7R 25 V 0 1 uF R1 5 0603 Chip Resistor 10 k L1 10 0603 Multi layer Chip Inductor 180 100 100 nH Sunlord SDCL L2 10 0603 Multi layer Chip Inductor 22 12 12 nH...

Page 6: ...haracteritic 31 1 24 COMP Characteristic 32 1 25 Temperature Sensor TS Characteristics 33 1 26 Rx Current VS Supply Voltage 33 1 27 Rx Current Voltage vs Temperature 34 1 28 Sensitivity vs Supply Volt...

Page 7: ...ynchronous receiver transmitter USART 68 5 13 Serial Perigheral Interface SPI 69 5 14 Synchronous Serial Interchip Sound I2S 70 5 15 General purpose input output GPIO 71 5 16 Analog to digital convert...

Page 8: ...Supply Voltage VDD 0 3 3 6 V Interface Voltage VIN 0 3 3 6 V Junction Temperature TJ 40 125 Storage Temperature TSTG 50 150 Soldering Temperature TSDR Retention at least 30 s 255 ESD Rating 2 Human b...

Page 9: ...Hz 13 dBm Direct Tie 23 mA FSK 433 MHz 10 dBm Direct Tie 18 mA FSK 433 MHz 10 dBm Direct Tie 8 mA FSK 868 MHz 20 dBm Direct Tie 87 mA FSK 868 MHz 20 dBm RF switch 80 mA FSK 868 MHz 13 dBm Direct Tie 2...

Page 10: ...33 dBc FRF 915 MHz 33 dBc RX Channel Bandwidth BW RX channel bandwidth 50 500 kHz Co channel Rejection Ratio CCR DR 10 kbps FDEV 10 kHz Interfere with the same modulation 7 dBc Adjacent Channel Rejec...

Page 11: ...MHz FRF 1 GHz 54 dBm 1 GHz to 12 75 GHz with harmonic 36 dBm Harmonic output for FRF 433 MHz 1 H2433 2nd harmonic 20 dBm POUT 46 dBm H3433 3nd harmonic 20 dBm POUT 50 dBm Harmonic output for FRF 868 M...

Page 12: ...Hz 127 170 MHz Synthesizer frequency resolution FRES 25 Hz Frequency tuning time TUNE 150 us Phase noise 433 MHz PN433 10 kHz frequency deviation 94 dBc Hz 100 kHz frequency deviation 99 dBc Hz 500 kH...

Page 13: ...o the crystal 1 9 Controller Reset and Power Control Module Specification Parameter Symbol Condition Min Typ Max Unit Rising VPVD PLS 3 0 0 1 8 1 88 1 96 V Falling PLS 3 0 0 1 7 1 78 1 86 Rising PLS 3...

Page 14: ...the flash memory is adjusted to the fHCLK frequency 0 wait period for 0 to 18 MHz 1 wait period for 18 to 36 MHz 2 waiting period for over 36 MHz The command pre fetch function is turned on notes thi...

Page 15: ...stop and sleep mode Parameter Symbol Condition Typ 1 Max Unit VDD 3 3V VDD 3 3V SLEEP mode current Kernel stopped all peripherals including Cortex M 0 core peripherals such as NVIC system ticking cloc...

Page 16: ...leep mode IDD External high speed clock HSE using AHB prefrequency to reduce the frequency 48 MHz 6 3 2 7 mA 24 MHz 3 7 2 0 8 MHz 1 8 1 2 Internal high speed RC oscillator 2 HSI AHB pre frequency to r...

Page 17: ...ternal user clock generated from external oscillation sources Low speed external user clock features Symbol Parameter Condition Min Typ Max Unit fLSE_ext User external clock frequency 0 32 768 1000 KH...

Page 18: ...rameter Condition Min Typ Max Unit fOSC_IN Oscillator frequency 4 8 20 MHz CL1 CL2 3 The suggested load capacitance and corresponding crystal serial resistance RS RS 30 20 pF i2 HSE drive current VDD...

Page 19: ...ecommended Usually CL1 and CL2 have the same parameters Crystal manufacturers usually give the parameters of the load capacitance as a serial combination of CL1 and CL2 Load capacitance CL is calculat...

Page 20: ...ency 25 calibration VDD 3 3 V 29 30 31 KHz VDD 1 8 V 5 5 V TA 40 105 24 30 36 KHz tSU LSI 3 LSI oscillator start time 30 80 s IDD LSI 3 LSI oscillator power consumption 0 2 A 1 Unless otherwise specif...

Page 21: ...ding to the PLL input clock frequency 1 16 FLASH characteristics FLASH characteristics Symbol Parameter Condition Min 1 Typ 1 Max 1 Unit tprog Word programming time 32 bit TA 40 85 175 s ERASE Page er...

Page 22: ...RPU Internal pull up resistor 3 3 1 8 40 100 k RPD Internal pull down resistor 3 3 1 8 40 100 k CIO I O pin capacitance 3 3 1 8 10 pF 1 The hysteresis voltage of the Schmitt trigger switching level Gu...

Page 23: ...6 11 8 22 14 22 5 44 100 11 5 19 5 36 17 5 26 7 52 Fast SR 0 25 4 6 9 14 10 5 18 36 50 7 3 11 20 12 3 20 40 100 15 18 5 33 16 25 47 10 V1 90 V1 10 V1 tr tf 50 V1 50 V1 tdr tdf 50 V1 50 V1 I O AC char...

Page 24: ...MHz 0 fTIMxCLK 2 MHz fTIMxCLK 48 MHz 0 24 MHz ResTIM Timer resolution fTIMxCLK 48 MHz 16 COUNTER Select the internal clock 16 bit counter clock cycle fTIMxCLK 48 MHz 1 65536 TIMxCLK fTIMxCLK 48 MHz 0...

Page 25: ...0 1Cb 300 120 ns tsu STO Establishment time of stop condition 1 4 0 0 6 0 26 s tw STO STA Time from stop condition to start condition bus idle 1 4 7 1 3 0 5 s Cb Capacity load per bus 1 400 400 200 pf...

Page 26: ...e SPI 1 19 84 ns SPI 2 20 5 tsu SI 1 Slave mode SPI 1 4 16 SPI 2 4 16 th MI 1 Data input retention time Master mode 0 ns th SI 1 Slave mode 4 ta SO 1 2 Data output access time Slave mode fPCLK 20 MHz...

Page 27: ...B out Bit 6 1 out MSB in Bit 6 1 in LSB out LSB in NSS input CLKPOL 0 MISO output MOSI input CLKPOL 1 ta SO tdis SO th NSS tsu NSS tw SCLKH tw SCLKL tr SCLK tf SCLK th SI tsu SI tv SO th SO CLKPHA 0 t...

Page 28: ...nit DuCy SCK I2S from the input clock duty cycle I2S Slave mode 30 50 70 fCLK 1 tc CLK I2S clock frequency Master mode 16 bit 2 Fs 3 16 Hz Master mode 16 bit 2 Fs 3 16 Master mode 32 bit 2 Fs 3 32 Sla...

Page 29: ...t n transmit Bit n receive Last bit transmit Last bit receive CLKPOL 0 WS input SD transmit CLKPOL 1 SD receive tsu WS tc CLK tw CLKH tw CLKL tv SD_ST th SD_ST tsu SD_SR th SD_SR th WS Last bit transm...

Page 30: ...connected to VDDA Formula 1 maximum RAIN formula RAIN TS fADC CADC ln 2N 2 RADC The above formula is used to determine the maximum impedence so that the error can be less than 1 4 LSB where N 12 repr...

Page 31: ...PAMP current consumption Common mode rejection ratio No load quiescent mode 0 5 mA CMMR Power supply rejection ratio 70 dB PSRR Gain bandwidth 60 dB GBW Conversion rate 2 5 MHz SR Minimum impedance lo...

Page 32: ...A 2 2 V normal mode 100 ns low speed mode 520 VOFFSET Comparator input offset error Full common mode range 4 20 mV Vhys Comparison of hysteresis voltage high speed low power consumption No hysteresis...

Page 33: ...DC sampling time when reading the temperature 1 87 6 43 s 1 Guaranteed by design and comprehensive evaluation not tested in production 2 The shortest sampling time can be determined by the application...

Page 34: ...z BR 10 Kbps Test Condition Freq 868 MHz Fdev 10 KHz BR 10 Kbps 7 0 7 3 7 5 7 8 8 0 8 3 8 5 8 8 9 0 9 3 9 5 40 25 85 Current Consumption mA Temperature Rx Current vs Volt Temp 3 3V 1 8V 3 6V 7 0 7 3 7...

Page 35: ...vs Tmeperature Test Condition FSK modulation DEV 10 KHz BR 10 Kbps 117 5 117 0 116 5 116 0 115 5 115 0 114 5 114 0 113 5 113 0 1 8 2 1 2 4 2 8 3 0 3 3 3 6 Sensitivity dBm Supply Voltage V Sensitivity...

Page 36: ...12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 2 2 1 2 0 1 9 1 8 Tx Power dBm Supply Voltage V Tx Power vs Supply Voltage 20dBm 13dBm 9 0 10...

Page 37: ...434 42 434 92 435 42 435 92 Power dBm center 433 92 MHz sweep 5s 2000pts Res BW 1 kHz 433 92 MHz Phase Noise output 13 dBm span 4 MHz att30 dB 12 4dBm 100 80 60 40 20 0 20 866 866 5 867 867 5 868 868...

Page 38: ...4 23 22 21 15 16 17 18 19 20 14 13 12 11 NC RFIP RFIN RFO RF_AVDD RF_DVDD RF_DGND GPIO3 GPIO1 GPIO2 XO XI NC PB7 RF_FCSB PB6 RF_CSB PB4 RF_SDA PB3 RF_SCLK PC13 PC14 MCU_NRST PC15 MCU_VDDA PA14 PA0 PA1...

Page 39: ...2380F64 QFN48 Pin Diagram Table 2 CMT2380F64 QFN40 QFN48 Pin description Pin name Pin number I O Description QFN 40 QFN 48 GND 0 0 Analog Chip substrate connected to GND NC 1 1 No connection RFIP RFIN...

Page 40: ...power supply PA0 14 14 20 IO MCU port PA0 USART1_CTS I Clearing signal is received in USART 1 flow control USART2_CTS I Clearing signal is received in USART 2 flow control USART2_RX I RxD of USART 2 L...

Page 41: ...TIM8_CH4 IO Timer8 I O input channel 4 TIM1_CH2 IO Timer1 I O input channel 2 SPI1_MISO IO SPI1 Master input slave output signal I2S_MCLK O I2S main clock signal LPUART_RX I RxD of LPUART COMP_INP Ana...

Page 42: ...mer 8 I O channel 2 EVENTOUT O Event output LPUART_RX I RxD of LPUART I2C2_SDA IO I2C2 serial data signal BEEPER_N_OUT O Beeper output USART2_CTS I Clearing signal of USART 2 flow control ADC_IN7 Anal...

Page 43: ...N I RTC reference clock input 50Hz or 60Hz PA8 25 31 IO MCU port PA 8 USART1_CK O USART 1 synchronous clock output signal TIM1_CH1 IO Timer 1 I O channel 1 EVENT_OUT O Event output MCO O Clock output...

Page 44: ...rt PA13 USART1_TX O TxD of USART 1 USART1_RX I RxD of USART 1 USART2_RX I RxD of USART 2 I2C1_SDA IO I2C1 serial data signal SPI1_SCK IO SPI1 clock signal I2S_CLK IO I2S serial clock signal SWDIO IO S...

Page 45: ...TIM8_CH4 IO Timer8 I O channel 4 BOOT0 43 Boot memory selection PB8 44 IO MCU port PB13 I2C1_SCL O I2C1 serial clock signal TIM8_CH1 IO Timer8 I O channel 1 NC 36 No connection XI 37 45 I 26 MHz crys...

Page 46: ...Bus Matrix MaX 48MHz DMA Flash System Bus DMA Flash Control SRAM ADC AHB System Bus1 HDIV SQRT RCC CRC AHB System Bus2 APB1 Max 48MHz PWR RTC IWDG WWDG OPA COMP TIM6 BEEPER TIM3 LPTIM USART2 LPUART I2...

Page 47: ...d provides a variety of digital communication interfaces including 3 U S ART 2 I2C 2 SPI and 1 I2S CMT2380F64 resources are shown as the following table Table 3 1 CMT 2380F64 External Resources Table...

Page 48: ...d is amplified by the limiting amplifier and then sent to the digital domain for digital demodulation During power on reset POR each analog block is calibrated to the internal reference voltage This a...

Page 49: ...oscillator LPOSC The CMT2380F64 rf system integrates a sleep timer driven by a 32 kHz low power oscillator LPOSC When this function is enabled the timer periodically wakes the chip from sleep When th...

Page 50: ...ted noise 2 SYM 2 SYM 1 SYM 1 SYM 1 SYM 1 SYM Figure 4 4 Received signal jump diagram The PJD mechanism defines that the input signal switching from 0 to 1 or from 1 to 0 is a phase jump Users can con...

Page 51: ...nges 4 10 Fast Frequncy Hopping The mechanism of fast frequency hopping is based on the frequency configured on the RFPDFK for instance 433 92 MHz during applications the MCU can simply change 1 or 2...

Page 52: ...e the two separated FIFO into one 64 byte FIFO It can be used both underTX and RX By configuring the FIFO_RX_TX_SEL to indicate whether it is currently used as TX FIFO or RX FIFO When the two FIFO are...

Page 53: ...g Transceivers provide a wealth of FIFO related interrupt sources as auxiliary means for efficient chip operation The FIFO interrupt timing sequence related to Rx and Tx is shown in the figure below 1...

Page 54: ...it for the crystal to stabilize the system before starting to work The default stability time is 2 48 ms which can be written to XTAL_STB_TIME 2 0 After modification the chip will stay in IDLE state u...

Page 55: ...almost all the modules are turned off SPI is open the registers of the configuration bank and control bank 1 will be saved and the contents filled in the FIFO before will remain unchanged However the...

Page 56: ...eeds to add the crystal start up and settled time Switching from other state to TFS will be completed immediately RX State All modules on the receiver will be opened in RX state Switching from RFS to...

Page 57: ...y can be configured to different GPIO mapping output Table 4 2 CMT2380F64 GPIO Pin No Name I O Function 48 GPIO1 IO Configurable as DOUT DIN INT1 INT2 DCLK TX RX RF_SWT 47 GPIO2 IO Configurable as INT...

Page 58: ...to the RX FIFO It is a pulse Auto RX_FIFO_OVF 01111 Indicates RX FIFO is overflow Auto TX_FIFO_NMTY 10000 Indicates that TX FIFO is not empty Auto TX_FIFO_TH 10001 Indicates the number of unread byte...

Page 59: ...PO1_SEL 1 0 GPIO1 0 Preamble OK Interrupt Source 0 Sycn Word OK Interrupt Source 0 Node ID OK Interrupt Source 0 CRC OK Interrupt Source 0 Packet OK Interrupt Source 0 Sleep Timeout Interrupt Source 0...

Page 60: ...E000_2000 0xE000_2FFF 0xE000_1000 0xE000_1FFF 0xE000_0000 0xE000_0FFF Reserved ROM Table 0xE010_0000 0xFFFF_FFFF 0xE00F_F000 0xE00F_FFFF COMP OPA Reserved TIM6 LPTIM Reserved TIM3 BEEPER 0x4000_2400 0...

Page 61: ...as well as three trigger types of rising edge falling edge or both edges and can also be independently shielded The suspend register holds the interrupt request of the status line and the correspondi...

Page 62: ...SCLK Max 48MHz ADCPLLPRES 4 ADC HCLK Prescaler 1 2 32 ADC_PLLCLK ADC_HCLK I2S_CLK ADC_CLK CKMOD ADC_CTRL3 HCLK FCLK CPU AHB BUS 8 SysTick DMA_CLK CRC_CLK APB1 Prescaler 1 2 4 8 16 TIM3 TIM6 If APB1 pr...

Page 63: ...he system is in 32 768 KHz low frequency operation mode SLEEP mode the core is stopped all peripherals including Cortex M0 core peripherals such as NVIC SysTick are still running STOP mode most of the...

Page 64: ...purpose timers The main functions of the basic timer are as follows 16 bit automatic reload accumulating counter 16 bit programmable can be modified in real time prescaler used to divide the input cl...

Page 65: ...counter start stop initialization or count by internal external trigger Input capture Output comparision Supports incremental quadrature encoder and Hall sensor circuits positioning Trigger input as a...

Page 66: ...d of a 16 bit auto loading counter driven by a programmable prescaler Supports multiple functions including measuring pulse width of the input signal input capture or generating output waveform output...

Page 67: ...entire system in the event of an application problem or as a free timer to provide timeout management for the application The option byte can be configured to be software or hardware enabled watchdog...

Page 68: ...EC value can be sent as the last byte in transmission mode A PEC error check for the last received byte SMBus 2 0 compatible Low timeout delay for 25 ms clock 10 ms master device cumulative clock low...

Page 69: ...data Four error detection flags Overflow error Noise error Frame error Check error 10 USART interrupt source with flag CTS change LIN break character detection Tx data register empty Tx complete Rece...

Page 70: ...ip Sound I2S I2S is a 4 pin synchronous serial interface communication protocol that can operate in master or slave mode It can be configured for 16 bit 24 bit or 32 bit transmission as well as input...

Page 71: ...maximum Supports software remapping the I O reusing function Support GPIO locking mechanism reset mode to clear the locked state Each I O port bit can be programmed arbitrarily but the I O port regist...

Page 72: ...83 Both rule conversion and injection conversion have external trigger options Discontinuous mode ADC power supply requirements 2 4 V to 3 6 V ADC input range 0 VIN VDDA During regular channel convers...

Page 73: ...In motor control applications it can be used in conjunction with the PWM output from the timer to form a cycle by cycle current control The main functions of the comparator are as follows 1 independe...

Page 74: ...calculation result according to a fixed generator polynomial In many applications CRC based technology is used to verify the consistency of data transmission or storage Within the scope of the EN IEC...

Page 75: ...CMT2380F64 www cmostek com 75 83 5 24 Serial wire SWD debug port SWD The ARM SWD Interface is embedded...

Page 76: ...QFN40 5x5 Make up with disk 1 8 to 3 6 V 40 to 85 3 000 Remarks 1 E represents the extended industrial product grade with supported temperature range from 40 to 85 Q represents package type of QFN40...

Page 77: ...83 www cmostek com 7 Package Outline Package information of CMT2380F64 is shown as followed D2 E2 b e L D E A A1 c Top View Bottom View Side View 1 1 40 40 2 N e K Nd 2 EXPOSED THERMAL PAD ZONE Figure...

Page 78: ...x5 package size Symbol Size millimeter mm Min Typ Max A 0 70 0 75 0 80 A1 0 0 02 0 05 b 0 15 0 20 0 25 b1 0 14REF C 0 18 0 20 0 25 D 4 90 5 00 5 10 D2 3 60 3 70 3 80 e 0 40 BSC Ne 3 60 BSC Nd 3 60 BSC...

Page 79: ...e 7 2 QFN48 6x6 package size Symbol Size mm Min Typ Max A 0 65 0 75 0 85 A1 0 0 02 0 05 A3 0 203 b 0 175 0 20 0 225 D 5 90 6 00 6 10 E 5 90 6 00 6 10 e 0 40 D2 4 20 E2 4 20 L 0 40 K 0 50 R 0 05 8 Silk...

Page 80: ...Laser Pin1 marking Circle diameter 0 3 mm Font size 0 5 mm right alignment First line silk printing 2380F64 Representative model CMT2380F64 Second line silk printing E9 Internal tracking code Third li...

Page 81: ...tion User Guide CMT2380F17 RF Low power design guidelines AN147 CMT2300A Special Function User Guide CMT2380F17RF feature function description AN149 CMT2300ARF Parameter Configuration Guide CMT2380F17...

Page 82: ...Revision History Table 10 1 Revision history Version Chapter Modify Date 0 1 All Initial 2022 05 13 0 2 All Added the QFN48 top view and package information 2022 07 11 0 3 1 12 Update the controller e...

Page 83: ...y is assumed for inaccuracies and specifications within this document are subject to change without notice The material contained herein is the exclusive property of CMOSTEK and shall not be distribut...

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