CMT2380F64
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Rev 0.3 | 15 / 83
Operating current
in the operating mode
I
DD
External clock
(2)
，
disable all
the peripherals
48 MHz
4.4
mA
24 MHz
3.2
8 MHz
2.6
1. Guaranteed by design and comprehensive assessment, not tested in production.
2. External clock, PLL is enabled when the f
HCLK
is 24 MHz or 48 MHz.
Maximum current consumption in sleep mode,
and the code runs in the internal flash memory
Parameter
Symbol
Condition
HCLK
Typ.
(1)
Unit
Working current in
sleep mode
I
DD
External clock
(2)
，
enable all the peripherals
48 MHz
6.5
mA
24 MHz
3.9
8 MHz
2.0
External clock
(2)
，
disable all the peripherals
48 MHz
2.9
24 MHz
2.1
8 MHz
1.4
1. According to the comprehensive assessment, V
DDmax
and f
HCLKmax
enabling peripheral are the test condition.
2. External clock, PLL is enabled when the f
HCLK
is 24 MHz or 48 MHz.
Typical consumption in stop and sleep mode
Parameter
Symbol
Condition
Typ
(1)
Max
Unit
V
DD
=3.3V
V
DD
=3.3V
SLEEP mode current
Kernel stopped, all peripherals including
Cortex-M 0 core peripherals such as NVIC,
system ticking clock (SysTick) still running
2.7
5
mA
STOP mode current
RTC is not running, SRAM, registers and all I/O
states retain
1.5
2.5
uA
PD mode current
VDD power down mode, 3 WAKEUP IO and
NRST can be awakened
0.5
1
uA
1.
Typ/ Max value is tested under TA=25
℃
.
⚫
Typical current consumption
MCU is under the following conditions
：
◼
All I / O pins are in input mode and are connected to a static level VDD or VSS with no load.
◼
All peripherals are disabled, unless otherwise noted.
◼
The access time of the flash memory is adjusted to the fHCLK frequency (0 wait period for 0 to 18 MHz, 1 wait
period for 18 to 36 MHz, 2 waiting period for over 36 MHz).
◼
The command pre-fetch function is turned on (notes: this parameter must be set before the clock and bus
frequency distribution is set).
◼
When the peripherals are turned on
：
f
PCLK1
= f
HCLK
, f
PCLK2
= f
HCLK
, f
ADCCLK
= f
PCLK2
/
3
.
f
