CMOSTEK CMT2380F64, Manual

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CMT2380F64
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SCLK
FCSB
SDA X X
FIFO read data
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 X
FIFO read data
CSB
> 1 SCLK cycle > 4 us > 2 us > 2 us > 1 SCLK cycle
Figure 4-7. SPI read FIFO timing
SCLK
FCSB
SDA
X X
FIFO write data
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 X
FIFO write data
CSB
> 1 SCLK cycle > 4 us > 2 us > 2 us > 1 SCLK cycle
Figure 4-8. SPI write FIFO timing
Transceivers provide a wealth of FIFO related interrupt sources as auxiliary means for efficient chip operation. The FIFO interrupt
timing sequence related to Rx and Tx is shown in the figure below.
1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24 27 26 29 28 31 30 EMPTY FULL
RX_FIFO_NMTY
RX_FIFO_TH
RX_FIFO_FULL
Sync 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 25 24 27 26 29 28 31 30 RX DATA Noise Noise
SYNC_OK
RX FIFO ARRAY
RX_FIFO_OVF
(FIFO_TH = 16)
RX_FIFO_WBYTE
Figure 4-9. Transceiver RX FIFO Interrupt Sequence Diagram