CMT2380F64
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Rev 0.3 | 28 / 83
SPI Sequnece diagram
– master mode
(1)
1. The measurement points are set at CMOS level: 0.3 VDD and 0.7 VDD.
I
2
S Charateristic
(1)
NSS input
CLKPHA=0
CLKPOL=0
MOSI output
MISO input
CLKPHA=0
CLKPOL=1
CLKPHA=1
CLKPOL=0
CLKPHA=1
CLKPOL=1
MSB out
Bit 6~1 out
LSB out
MSB in
Bit 6~1 in
LSB in
t
r(SCLK)
t
f(SCLK)
t
h(MO)
t
v(MO)
t
w(SCLKH)
t
w(SCLKL)
t
su(MI)
t
h(MI)
t
c(SCLK)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DuCy
(SCK)
I2S from the
input clock duty cycle
I2S Slave mode
30
50
70
%
f
CLK
1/t
c(CLK)
I2S clock
frequency
Master mode (16 bit)
-
2*Fs
(3)
*
16
-
Hz
Master mode (16 bit)
-
2*Fs
(3)
*
16
-
Master mode (32 bit)
-
2*Fs
(3)
*
32
-
Slave mode (32 bit)
-
2*Fs
(3)
*
32
-
t
r(CLK)
I2S clock up and
down time
Load capacitance: CL = 50 pF
-
-
8
ns
t
v(WS)
(1)
WS validity
time
Master mode
13.5
-
-
t
h(WS)
(1)
WS retention
time
Master mode
0
-
-
t
su(WS)
(1)
WS
establishment time
Slave mode
4
-
-
t
h(WS)
(1)
WS retention
time
Slave mode
0
-
-
t
w(CLKH)
(1)
CLK high and low
time
Master mode, f
PCLK
= 16 MHz,
audio 48 kHz
312.5
-
-
t
w(CLKL)
(1)
345
-
-
t
su(SD_MR )
(1)
Data
time
entry setup
master receiver
3.6
-
-
t
su(SD_SR)
(1)
Slave receiver
3.5
-
-
