CMT2380F64
www. cmostek. com
Rev 0.3 | 52 / 83
To be noticed, when reading a register, both of the controller and the transceiver will switch the IO (SDA) port between address 0
and data 7. In this case, the SDA switches the I/O port from input to output, and the controller switches the corresponding I/O
port from output to input. Note the dotted line in the middle. It is strongly recommended that the controller switch the I/O port to
input before sending out the falling edge of the SCLK. The transceiver does not switch the IO to output until it sees the falling
edge. This avoids the electrical conflict caused by both setting SDA as output.
SCLK
CSB
SDA
X
0
1
2
3
4
5
6
7
X
register address
register read data
0
1
2
3
4
5
6
7
r/w = 1
FCSB
> 0.5 SCLK cycle
> 0.5 SCLK cycle
Figure 4-5. SPI read register timing
SCLK
CSB
SDA
X
X
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
register address
register write data
FCSB
r/w = 0
> 0.5 SCLK cycle
> 0.5 SCLK cycle
Figure 4-6. SPI write register timing
4.11.2
FIFO Interface
CMT2380F64 provides two separated 32-byte FIFO by defaul for RX and TX respectively.
RX FIFO is used to store the received
data in RX mode and TX FIFO is used to store the transmitting data in TX mode.
Users can also set FIFO_MARGE_EN to1 to
merge the two separated FIFO into one 64-byte FIFO. It can be used both underTX and RX. By configuring the FIFO_RX_TX_SEL
to indicate whether it is currently used as TX FIFO or RX FIFO. When the two FIFO are not merged, users can fill in the next time 32
byte TX FIFO while the 32 byte RX FIFO is filled in the RX mode to save operation time.
The FIFO can be accessed via the SPI interface. The user can clear the FIFO by setting FIFO_CLR_TX or FIFO_CLR_RX to 1.
Also, the user can re-send the old data in the TX FIFO by setting FIFO_RESTORE to 1, without the need of re-filling the data.
When the MCU accesses to the FIFO, the user must first configure a few registers to set up the FIFO read/write mode, as well as
some other working mode. The details are introduced in
“AN143-CMTT2380F64 FIFO and Data Packet Usage Guideline”
. Here is
the read-write timing diagram. Note that there is a slight difference in the control of the FCSB for accessing to the FIFO and the
control of the CSB for accessing to the register. When the MCU starts to access to the FIFO, FCSB must be pulled down 1-clock
cycle at first, and then send the rising edge of SCL. After the last falling edge of SCL is sent, the MCU must wait at least 2 us to pull
up the FCSB. Between the adjacent read/write operations, the FCSB must be pulled high for 4us at least. When writing the FIFO,
the first bit data must be ready 0.5 clock cycles before sending the first rising edge of SCL.
