CMT2380F64
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Rev 0.3 | 24 / 83
Symbol
Parameter
VDD
Min
Typ
Max
Unit
1. The reset network is to prevent parasitic reset.
2.
Users must ensure that the potential of the NRST pin can be lower than the maximum VIL (NRST), otherwise the MCU
cannot be reset.
Filter
V
DD
Internal
reset
MCU_NRST
NRST pin protection recommended circuit design
1.19
TIM characteristic
TIMx
(1)
Characteristic
Symbol
Parameter
Conditions
Min
Max
Unit
t
res(TIM)
Timer resolution time
f
TIMxCLK
= 48 MHz
1
-
TIMxCLK
f
TIMxCLK
= 48 MHz
20.8
-
ns
EXT
Timer external clock frequency from CH1 to
CH2
f
TIMxCLK
= 48 MHz
0
f
TIMxCLK
/2
MHz
f
TIMxCLK
= 48 MHz
0
24
MHz
Res
TIM
Timer resolution
f
TIMxCLK
= 48 MHz
-
16
位
COUNTER
Select the internal clock, 16-bit counter clock
cycle
f
TIMxCLK
= 48 MHz
1
65536
TIMxCLK
f
TIMxCLK
= 48 MHz
0.0208
1365
μs
t
MAX_COUNT
Maximum count
f
TIMxCLK
= 48 MHz
-
65536x65536
TIMxCLK
f
TIMxCLK
= 48 MHz
-
89.478
s
1. TIMx is a common name and stands for TIM1~TIM8.
1.20
I2C Characteristic
The I2C interface complies with the standard I2C communication protocol while SDA and SCL are not "true" open-drain
pins. When configured as open-drain output, the PMOS tube between the pin and VDD will be turned off, but still exists.
The I2C interface characteristic is shown as the following table. As for the specification of I/O reset function pins (SDA and
SCL), please refer to chapter 1.17.
t
f
t
t
t
