Altigen Altiware OE 4.5, System Administration & Installation Manual, Page: 192 / 455

Board Configuration
AltiWare OE System Installation & Administration Manual 163
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• Xmt Frame Slips - Transmit Frame Slips counter shows the number
of frame slips for the transmitter.
• Clear button - use the Clear button to reset the statistics counters.
Note: For ideally synchronized systems, Transmit and Receive
Frame Slips counters should be ‘0.’ Continuous update of the
frame slips counters means that transmit and receive
frequencies are not equal. In this case, you should check the
system and MVIP clock setup.
Setting the Configurable Options
• You can set the Operating Mode to either T1 or E1.
• You can set the Frame Type to either SF or ESF.
SF (Superframe Format) consists of twelve (12) consecutive frames.
ESF (Extended Superframe Format) consists of twenty-four (24)
consecutive frames.
• You can set the Line Code to either AMI or B8ZS.
AMI (Alternate Mark Inversion) is the line coding format in T1
transmission systems whereby successive ones (marks) are alternately
inverted and sent with opposite polarity of the preceding mark. B8ZS
(Binary 8 Zero Substitution) sends two violations of the bipolar line
encoding technique, rather than inserting a one for every seven
consecutive zeros.
• You can set the Zero Code Suppression to None (default setting),
Jam Bit 8, GTE or Bell.
Zero Code Suppression inserts a “one” bit to prevent the transmission
of eight or more consecutive “zero” bits; Jam Bit 8 forces every bit 8
to a one; GTE Zero Code Suppression replaces bit 8 of an all zero
channel byte to a one, except in signaling frames where bit 7 is forced
to a one. Bell Zero Code Suppression replaces bit 7 of an all zero
channel byte with a one.
• If you click the T1/PRI Configuration button you can set channels to
either T1 or PRI, as discussed in “Setting up T1 or PRI Channels on
the Triton T1/PRI Board” on page 165.
• You can set the System Clock Master if you have a back-to-back
configuration and you want this span to be the master clock to the
system. (Only one clock master should be selected in a back-to-back
system.) See the following discussion.