Ziatech Corporation ZT 8905, Руководство по оборудованию

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Chapter 3. STD Bus Interface
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Extended Architecture
Extended Architecture 8-, 16-, and 32-bit peripherals are referred to as EA8, EA16, and EA32,
respectively. The ZT 8905 supports interfacing to all three data width types. The ZT 8905 dynamically
senses the type of peripheral at the start of the backplane cycle and will scale the transfer to match
the data width of the peripheral. The memory addressing for EA peripherals is 32 bits (4 Gbytes); I/O
addressing is 16 bits (64 Kbytes). EA cycles are typically completed in three STD 32 clock periods.
Multiprocessing
In addition to the different data transfer modes, the STD 32 system has another advantage: it
supports up to seven processor boards in a single system. With the addition of an STD bus arbiter,
such as the ZT 89CT39, multiple ZT 8905 boards have fixed or rotating priority access to STD bus
memory and I/O resources. This architecture is useful for applications that can be divided into
modular control blocks, with each module running on a unique ZT 8905. Ziatech manufactures
several boards that are compatible with the multiprocessing architecture.
STD 32 Compliance Levels
STD 32 features are discussed in terms of compliance levels. The compliance codes can be used to
determine the general capabilities of a board, particularly when configuring a system composed of
boards from different manufacturers.
Permanent Master: EA32, EA16, EA8, SA16, SA8-{MD}, I, SDMA8, SDMA16, SDMABP
Temporary Master: SA16, SA8-{MX}, I, SDMA8, SDMA16, SDMABP
The following are brief descriptions of the STD 32 compliance levels supported by the ZT 8905.
EA8, EA16, EA32 Supports 8-bit, 16- and 32-bit data transfers with STD 32 Extended Architecture
signal format and timings. The ZT 8905 automatically determines the width of
the data transfer at the start of each STD bus operation. Memory addresses are
32 bits wide (4 Gbytes), and I/O addresses are 16 bits wide (64 Kbytes).
SA8, SA16 Supports 8-bit and 16-bit data transfers with STD-80 signal format and timings.
The ZT 8905 automatically determines the width of the data transfer at the start
of each STD bus operation. STD-80 compatible memory and I/O boards are
supported.
I Supports four additional STD bus interrupts: INTRQ1*, INTRQ2*, INTRQ3*, and
INTRQ4*. These interrupts are input from the STD bus and connected to the
interrupt controller through a software configurable switch. This feature is
supported by the BIOS SETUP program.
{MX} Supports the multiple master (MREQx*, MAKx*) protocol. These two signals are
used by the ZT 8905 in a multiple master architecture to gain control of STD bus
resources. The use of these signals requires a bus arbiter, such as the
ZT 89CT39, to be plugged into Slot X. The ZT 8905 requires Revision D or
higher of the ZT 89CT39.
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