Ziatech Corporation ZT 8905, Руководство по оборудованию

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Chapter 4. Interrupt Controller
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INTERRUPT SOURCES
The interrupt sources are summarized below.
Backplane: There are five STD bus interrupts routed to the interrupt configuration selection logic:
INTRQ*, INTRQ1*, INTRQ2*, INTRQ3*, and INTRQ4*. These interrupts are active-low
on the STD bus and inverted before they reach the interrupt configuration logic.
Frontplane: Two of the five frontplane interrupts are routed to the interrupt configuration logic.
These interrupts are available through the multi-I/O connector J5 as active-low inputs
that are inverted before reaching the interrupt configuration logic. The remaining three
frontplane interrupts are directly tied to the interrupt controller, after being logically
inverted. The pin assignments for connector J5 are given in Appendix B. Many STD
bus boards support a 10-pin header connector for routing interrupts to the ZT 8905
through a ribbon cable. This architecture is useful if the application requires more
interrupts than are available on the STD bus backplane.
PCI: Four interrupt levels may be assigned to the PCI bus when not used for other devices.
IR5, IR6, IR9, and IR14 may be allocated to PCI through screen 2 of the BIOS SETUP
utility. For more on the BIOS SETUP utility, see the section "BIOS SETUP Overview" in
Appendix A. The PCI configuration utility then assigns interrupts to PCI devices as
needed. In STAR SYSTEMs, IR5 is not available for PCI allocation. If an STD 32 floppy
disk controller is used, IR6 is not available for PCI use.
Local: Local interrupt sources include the keyboard controller, serial ports (COM1, COM2),
multiprocessor communications, 1284 parallel port, real-time clock, timer/counters,
DMA controller, Math coprocessor, watchdog timer, and optional IDE controller.
PROGRAMMABLE REGISTERS
Each interrupt controller includes four initialization registers, three control registers, and three status
registers. The I/O port addressing for the interrupt controllers is given in the "Interrupt Controller
Register Addressing" table below. The base address of the master interrupt controller is 20h and the
base address of the slave interrupt controller is A0h.
Interrupt Controller Register Addressing
Address Register Operation
Base+0h IRR, ISR, IPR Read
Base+0h ICW1 Write
Base+0h OCW2, OCW3 Write
Base+1h OCW1 Read/Write
Base+1h ICW2, ICW3, ICW4 Write
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