Ziatech Corporation ZT 8905, Руководство по оборудованию

Страница: 16 / 166

ILLUSTRATIONS
Functional Block Diagram ...................................................................................................................... 4
J5 Multi-I/O Connector............................................................................................................................ 8
Memory Address Map .......................................................................................................................... 13
I/O Address Map................................................................................................................................... 14
Connector Locations...................................................................................................................... 15, 97
Socket T6C Location ............................................................................................................................ 16
BIOS SETUP Utility: Screen 1 ....................................................................................................... 18, 84
BIOS SETUP Utility: Screen 2 ....................................................................................................... 18, 84
STD Bus Polled Interrupt Structure ...................................................................................................... 25
STD Bus Vectored Interrupt Structure.................................................................................................. 25
Non-Maskable Interrupt Structure ........................................................................................................ 26
Multiple Master Architecture ................................................................................................................. 27
Intelligent I/O Architecture .................................................................................................................... 28
Socket T6C Location ............................................................................................................................ 29
Interrupt Architecture ............................................................................................................................ 32
Interrupt Initialization Programming...................................................................................................... 34
Initialization Register ICW1 .................................................................................................................. 35
Initialization Register ICW2 .................................................................................................................. 35
Master Initialization Register ICW3 ...................................................................................................... 35
Slave Initialization Register ICW3 ........................................................................................................ 35
Initialization Register ICW4 .................................................................................................................. 36
Operational Register OCW1................................................................................................................. 36
Operational Register OCW2................................................................................................................. 37
Operational Register OCW3................................................................................................................. 38
Status Register IRR.............................................................................................................................. 38
Status Register ISR .............................................................................................................................. 39
Status Register IPR .............................................................................................................................. 39
Extended Mode Register ...................................................................................................................... 40
Counter/Timer Architecture .................................................................................................................. 41
Count Register High Byte ..................................................................................................................... 43
Count Register Low Byte ...................................................................................................................... 43
Status Register ..................................................................................................................................... 43
General Control Register...................................................................................................................... 44
Count Latch Control Register ............................................................................................................... 44
Multiple Latch Control Register ............................................................................................................ 45
DMA Architecture ................................................................................................................................. 48
Address Register (8-bit I/O).................................................................................................................. 50
Address Register (16-bit I/O)................................................................................................................ 50
Count Register...................................................................................................................................... 50
Status Register ..................................................................................................................................... 51
Command Register .............................................................................................................................. 51
Write Request Register ........................................................................................................................ 52
Write Single Mask Register .................................................................................................................. 52
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com