Chapter 3. STD Bus Interface
30
Multiple Master Reset
In a multiple master system, a ZT 8905 configured as a permanent master operates the same as a
ZT 8905 operating in a single master architecture. The permanent master monitors Vcc with a
precision voltage monitoring circuit and holds the system in reset when Vcc is below 4.75 V. The
permanent master also will hold the system in reset when either the on-board pushbutton reset is
asserted or the STD 32 bus signal PBRESET* (P48) is asserted. The permanent master asserts
SYSRESET* (P47) to hold the system in reset.
A ZT 8905 configured as a temporary master manages reset differently. A temporary master does
not monitor PBRESET* and does not generate SYSRESET*. Instead, a temporary master ignores
PBRESET* and monitors SYSRESET*. This enables the temporary masters to be reset when the
permanent master generates SYSRESET*. This also enables the pushbutton reset on the temporary
master to reset only the temporary master while the pushbutton on the permanent master resets the
entire system.
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Содержание ZT 8905
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