Ziatech Corporation ZT 8905, Руководство по оборудованию

Страница: 38 / 166

CHAPTER 3. STD 32 BUS INTERFACE
The ZT 8905 includes several I/O devices common to industrial control applications. The ZT 8905
also operates with the STD 32 bus architecture to support additional I/O and memory mapped
devices as required by the application. This chapter discusses the STD 32 architecture and its effect
on the operation of the ZT 8905.
STD 32 BACKGROUND
The STD-80 Series Bus Specification , developed in the early 1980s by Ziatech Corporation, defines
the electrical, mechanical, and functional characteristics of an STD bus system based on the 8088
series of microprocessors. Features of an STD-80 system include an 8-bit data bus, 24-bit address
bus, and single bus master operation.
In the late 1980s, Ziatech developed the STD 32 Bus Specification and Designer's Guide as an
extension to the STD-80 Series Bus Specification . Features of an STD 32 system include
compatibility with STD-80 memory and I/O boards, expansion capabilities of up to a 32-bit data bus
and a 32-bit address bus, and support for multiple bus master operation.
STD-80 PERIPHERAL SUPPORT
The ZT 8905 is electrically compatible with Revision 2.3 of the
STD-80 Series Bus Specification
(Ziatech part number ZT MSTD80), allowing peripherals that were designed for that specification to
be used with the ZT 8905 in an STD 32 backplane. The ZT 8905 cannot be used in an STD-80
backplane because of the additional signals needed for EA 32-bit addressing. However, STD-80
boards can be used with the ZT 8905 in an STD 32 backplane. STD-80 superset features supported
by the ZT 8905 include:
•
A 24-bit address bus
•
Four additional maskable interrupts
•
Dynamically driven I/O expansion
•
DMA slave support
The following topics discuss these features.
Address Multiplexing
The STD-80 Series Bus Specification defines a multiplexing scheme to transfer address lines A16
through A19 across the lower half of the data bus during the start of each memory cycle. The
ZT 8905 extends this concept by also transferring address lines A20 through A23 across the upper
half of the data bus.
This feature is especially useful if all memory mapped STD bus boards used in the system decode
24 bits of address. If a memory mapped board decodes fewer than 24 bits, the board appears
multiple times in the 24-bit memory map.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com