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Chapter 3. STD Bus Interface

27

Multiple Master

A multiple master architecture requires one permanent master and one or more temporary masters,
as illustrated in the "Multiple Master Architecture" figure below. The ZT 8905 is configurable for either
permanent or temporary master operation. Each master has complete access to STD bus resources
and operates at full speed when the local CPU is communicating with local memory and I/O. It is not
until the application software attempts an STD bus access that arbitration occurs.

The ZT 8905 responds to an STD bus access from the application software by generating an
STD bus request, MREQx* (E70), to an external bus arbiter, such as the ZT 89CT39. The
ZT 89CT39 must be Revision D or higher. The ZT 8905 then suspends all local operation until the
bus arbiter returns an STD bus acknowledge, MAKx* (E69). All arbitration is done in hardware on the
external bus arbiter board and is transparent to the application software. The amount of time required
for this arbitration depends on the amount of time higher priority masters are in control of STD bus
resources. A shared resource locking mechanism is supported to guarantee exclusive access to
STD bus memory or I/O.

I/O SLAVE

MEMORY SLAVE

ZT 8905

TEMPORARY

MASTER

ZT 8905

TEMPORARY

MASTER

ZT 8905

TEMPORARY

MASTER

ZT 8905

PERMANENT

MASTER

SLOT X

ARBITER

TM

ZT200

Embedded
Computer

Multiple Master Architecture

Intelligent I/O

An intelligent I/O system includes a single ZT 8905 and one or more intelligent I/O boards, such as
the ZT 8832. This architecture is illustrated in the "Intelligent I/O Architecture" figure on the following
page. The intelligent I/O board incorporates several I/O devices, a dual-port RAM for processor
communications, and a CPU dedicated to controlling these devices.

Each intelligent I/O board operates at full speed when communicating with local memory, local I/O,
and dual-port RAM. The ZT 8905 also operates at full STD bus speeds when accessing the dual-port
RAM. It is not until the ZT 8905 and the intelligent I/O board access the dual-port RAM at the same
time that arbitration occurs.

All arbitration is done in hardware local to each intelligent I/O board, eliminating the need for an
external bus arbiter. The arbitration is transparent to the application software. The amount of time
required for arbitration depends on the amount of time the device in control of the dual-port RAM
requires to complete operation. A shared resource locking mechanism is supported to guarantee
exclusive access to dual-port RAM by either the ZT 8905 or the intelligent I/O board.

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Содержание ZT 8905

Страница 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Страница 2: ...R E M A N U A L For ZT 8905 Revision A 3 Single Board Computer with Pentium Processor For ZT 8906 Revision A 3 ZT M8905 September 9 1997 102575 Artisan Technology Group Quality Instrumentation Guaran...

Страница 3: ...se Drive Suite 110 A 319 North Pottstown Pike Suite 107 P O Box 110 Austin TX 78752 USA Exton Pennsylvania 19341 USA AC SON Tel 512 458 3177 Tel 610 524 9070 Netherlands 5690 FAX 512 458 3178 FAX 610...

Страница 4: ...R E M A N U A L For ZT 8905 Revision A 3 Single Board Computer with Pentium Processor For ZT 8906 Revision A 3 ZT M8905 September 9 1997 102575 Artisan Technology Group Quality Instrumentation Guaran...

Страница 5: ...X is a registered trademark of Quantum Software Systems Ltd STD 32 is a registered trademark of Ziatech Corporation STD 32 STAR SYSTEM is a trademark of Ziatech Corporation UNIX is a registered tradem...

Страница 6: ...controllers programmable registers Chapter 5 Counter Timers discusses the three programmable counter timers It includes a diagram of the counter timer architecture a summary of operating modes and de...

Страница 7: ...x B Specifications contains the electrical environmental and mechanical specifications for the ZT 8905 It also provides illustrations of cables and connector pinouts and tables showing connector pin a...

Страница 8: ...E 1284 Parallel Port Printer Interface 8 Speaker Interface 9 Optional IDE Interface 9 CHAPTER 2 GETTING STARTED 11 UNPACKING 11 WHAT S IN THE BOX 11 SYSTEM REQUIREMENTS 11 MEMORY CONFIGURATION 12 I O...

Страница 9: ...ICW4 36 Operational Registers OCW1 OCW3 36 Operational Register OCW1 36 Operational Register OCW2 37 Operational Register OCW3 38 Status Registers IRR ISR IPR 38 Status Register IRR 38 Status Registe...

Страница 10: ...63 Divisor Latch LSB and MSB 64 Interrupt Control Register 64 Interrupt Status Register 65 Line Control Register 65 Line Status Register 66 Modem Control Register 66 Modem Status Register 67 ADDITION...

Страница 11: ...ter to ZT 8911 88 W2 W3 Reserved 88 CUTTABLE TRACE OPTIONS AND LOCATIONS 88 CT1 CT2 Frontplane DMA 89 APPENDIX B SPECIFICATIONS 91 ELECTRICAL AND ENVIRONMENTAL 91 Absolute Maximum Ratings 91 DC Operat...

Страница 12: ...107 Five Year Limited Warranty 107 Special Extended Warranty Option 108 Life Support Policy 108 APPENDIX D PCI CONFIGURATION SPACE MAP 109 Artisan Technology Group Quality Instrumentation Guaranteed 8...

Страница 13: ...Contents Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 14: ...Register Addressing 57 Serial Controller Register Addressing 62 Baud Rate Divisors Table 63 Pentium Processors Maximum Ambient Temperatures 92 STD Bus Loading P Connector 94 STD Bus Loading E Connect...

Страница 15: ...Tables Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 16: ...tialization Register ICW3 35 Slave Initialization Register ICW3 35 Initialization Register ICW4 36 Operational Register OCW1 36 Operational Register OCW2 37 Operational Register OCW3 38 Status Registe...

Страница 17: ...Line Status Register 66 Modem Control Register 66 Modem Status Register 67 Line Printer Data Register 70 Line Printer Status Register 71 Line Printer Control Register 71 System Register 0 75 System Re...

Страница 18: ...eral operation is provided by an on board PCI expansion interface ZT 8906 The ZT 8906 is physically a ZT 8905 with a three slot CompactPCI enclosure attached to it This enclosure allows high speed PCI...

Страница 19: ...r initializing shared memory and other system I O on behalf of any Temporary Masters The STAR BIOS manages all of the system initialization FEATURES OF THE ZT 8905 STD 32 bus compatible PCI compatible...

Страница 20: ...n the ZT 8905 The DOS system provides a development platform similar to a PC enabling applications to be developed quickly DOS includes support for many of the ZT 8905 peripherals and is supported by...

Страница 21: ...rial Ports IEEE 1284 Parallel Port Local Bus Expansion Connector ZT 8905 Pentium CPU 16 Kbyte Cache 32 Bit Bus Interface Single and Multiple Master Operation Four 32 Bit DMA Channels Interrupt Control...

Страница 22: ...at higher frequencies and lower power than did the first generation Pentium P5 The ZT 8905 operates the external microprocessor bus at either 50 60 or 66 MHz The P54C operates internally at 1 5x 2x 2...

Страница 23: ...The ZT 8905 supports high speed peripheral interfacing via a PCI mezzanine interface The mezanine is implemented through a high density 2 mm connector provided by the ZT 8905 32 bit PCI is supported...

Страница 24: ...nter timers include interrupt on count frequency divider square wave generator software triggered hardware triggered and one shot See Chapter 5 Counter Timers for more information DMA Two enhanced 823...

Страница 25: ...EEE 1284 Parallel Port Printer Interface The ZT 8905 includes an IEEE 1284 compatible parallel port for connection to a printer or other parallel port devices such as software keys required by many ap...

Страница 26: ...operation where it is desired to have a local boot device that is independent of other STAR SYSTEM CPUs This option includes a 2 5 IDE interface mounted on a carrier board which is attached to the bot...

Страница 27: ...Chapter 1 Introduction 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 28: ...ist ZT 8905 8906 Single Board Pentium Computer in anti static bag save the anti static bag for storing or returning the ZT 8905 8906 On Line Help disk for ZT 8905 8906 Optional PCI peripherals Optiona...

Страница 29: ...emory architecture of the Pentium processor Each layer of DRAM up to three layers must be configured differently to allow the stacked module to provide discrete addressing for the layer pair Additiona...

Страница 30: ...this chapter During local I O operations the STD bus is held static to decrease system electrical noise and power consumption STD bus I O is supported through either Standard Architecture SA8 or SA16...

Страница 31: ...3F7h PCI 3F8 3FFh 400 3FFFh 4000 4FFFh 5000 BFFFh C000 CFFFh D000 DFFFh E000 FFFFh VGA Registers Floppy IDE Registers COM1 PCI or STD 32 PCI Config STD 32 or PCI set by VGA location PCI STD 32 or PCI...

Страница 32: ...ards should refer to the Revision 0 manual for connector and cabling information Connector Assignments ZT 8905 Boards Revision A and Higher Connector Function J1 Optional L2 cache module J2 Fan Connec...

Страница 33: ...ility is executed during the boot sequence when the s key is typed In DOS systems SETUP may be executed by running the SETUP COM program from the command line The BIOS SETUP utility on all Ziatech CPU...

Страница 34: ...ow Screen 1 Generic option list Screen 1 lists the options shared among all Ziatech CPUs Base memory and extended memory size selection boot source hard disk type and floppy disk type are configurable...

Страница 35: ...the current parameters or ESC to quit Ziatech Industrial BIOS Setup Utility 2482 16 63 ZT8905F02 05 BIOS SETUP Utility Screen 1 Generic SETUP Options Copyright C 1997 Ziatech Corporation Interrupt fro...

Страница 36: ...ETUP to query the drive to determine the correct geometry cylinders heads sectors 2 Select the proper boot source in the SETUP utility depending on the OS installation media that will be used For exam...

Страница 37: ...Chapter 2 Getting Started 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 38: ...05 is electrically compatible with Revision 2 3 of the STD 80 Series Bus Specification Ziatech part number ZT MSTD80 allowing peripherals that were designed for that specification to be used with the...

Страница 39: ...three DMA slaves controlled via a 10 pin frontplane header provided by the ZT 90205 cable STD 32 BUS COMPATIBILITY The ZT 8905 is compatible with the STD 32 Bus Specification and Designer s Guide Ziat...

Страница 40: ...system composed of boards from different manufacturers Permanent Master EA32 EA16 EA8 SA16 SA8 MD I SDMA8 SDMA16 SDMABP Temporary Master SA16 SA8 MX I SDMA8 SDMA16 SDMABP The following are brief descr...

Страница 41: ...request signal to determine which is requesting service This procedure is fine for most applications provided that each source can be polled and that the interrupt controller is programmed for level...

Страница 42: ...PORT STD Bus Polled Interrupt Structure STD BUS INTERRUPT SOURCE 1 INTERRUPT SOURCE 2 INTERRUPT SOURCE 3 ZT 8905 INTRQ INTRQ1 INTRQ2 INTRQ INTERRUPT STATUS PORT INTRQ1 INTRQ2 INTERRUPT SOURCE 4 INTERR...

Страница 43: ...below 3 0 V Other sources of reset include the watchdog timer local pushbutton switch and the STD bus pushbutton reset signal PBRESET P48 The ZT 8905 responds to any of these reset sources by initial...

Страница 44: ...MPORARY MASTER ZT 8905 TEMPORARY MASTER ZT 8905 TEMPORARY MASTER ZT 8905 PERMANENT MASTER SLOT X ARBITER TM ZT200 Embedded Computer Multiple Master Architecture Intelligent I O An intelligent I O syst...

Страница 45: ...ementations require an STD bus memory slave for communications between the masters With an intelligent I O architecture all communications between the single master and the intelligent I O boards are...

Страница 46: ...ne 16 bit board e g ZT 8902 then only one of the ZT 8905 temporary masters can have RP1 installed An STD 32 backplane is required A ZT 89CT39 ZT 8911 CPU arbiter or equivalent bus arbiter is needed to...

Страница 47: ...gnal PBRESET P48 is asserted The permanent master asserts SYSRESET P47 to hold the system in reset A ZT 8905 configured as a temporary master manages reset differently A temporary master does not moni...

Страница 48: ...rupts Jumperless configuration Level triggered or edge triggered recognition Fixed or rotating priorities PCI Interrupt support PCI Extended Mode register support The interrupt architecture is illustr...

Страница 49: ...STD 32 INTRQ1 STD 32 INTRQ2 J5 PIN4 STD 32 INTRQ STD 32 INTRQ1 STD 32 INTRQ3 STD 32 INTRQ4 STD 32 INTRQ PCI STD 32 INTRQ2 STD 32 INTRQ PCI ONBOARD LPT STD 32 INTRQ STD 32 INTRQ1 STD 32 INTRQ STD 32 IN...

Страница 50: ...es IR5 IR6 IR9 and IR14 may be allocated to PCI through screen 2 of the BIOS SETUP utility For more on the BIOS SETUP utility see the section BIOS SETUP Overview in Appendix A The PCI configuration ut...

Страница 51: ...iven in the Interrupt Initialization Programming figure ICW1 ICW2 and ICW3 must be programmed during each initialization sequence ICW4 may or may not be programmed as required by the application ICW1...

Страница 52: ...5 4 3 2 1 0 Register ICW2 Address Base 1 Vector Pointer 0 Access Write Vector Upper 5 bits of pointer 0 0 Initialization Register ICW2 Initialization Register ICW3 Register Master ICW3 Address Base 1...

Страница 53: ...anaged by three 8 bit operational registers These registers are programmed in any sequence for things such as enabling and disabling interrupt requests and changing interrupt priorities Illustrations...

Страница 54: ...5 110 IR6 111 IR7 Operational mode End of Interrupt 001 Non specific 011 Specific Automatic Rotation 101 Rotate on non specific 100 Rotate on automatic set 000 Rotate on automatic reset Specific Rotat...

Страница 55: ...mask 0 P Poll Command 0 No poll 1 Poll 11 Special mask Operational Register OCW3 Status Registers IRR ISR IPR Each interrupt controller includes three status registers A status register is selected b...

Страница 56: ...ister ISR Status Register IPR Active 0 7 6 5 4 3 2 1 0 Register IPR Address Base 0 Highest Active Request Access Read 000 IR0 0 0 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 Interrupt 0 In...

Страница 57: ...1 Level triggered 0 Edge triggered 1 Level triggered 0 Edge triggered 1 Level triggered 0 Edge triggered 1 Level triggered 0 Edge triggered 1 Level triggered Extended Mode Register ADDITIONAL INFORMAT...

Страница 58: ...l counter timers are available for application development In an MS DOS system for example counter timer 0 generates a periodic system interrupt and should not be programmed by the application Please...

Страница 59: ...ount values are written and both the count and status information is read The Control register occupies the remaining I O port address which services all three counter timers Counter Timer Register Ad...

Страница 60: ...is chapter 7 6 5 4 3 2 1 0 Register Status Address 40h Channel Count Format BCD Access Write Access 0 Binary Select Mode 1 BCD Operating Mode 000 Terminal count interrupt Mode 0 001 Retriggerable one...

Страница 61: ...unt interrupt 001 Retriggerable one shot 010 Rate generator 011 Square wave generator 100 Software strobe 101 Hardware strobe 110 Same as 010 111 Same as 011 Access Mode 00 Count latch command 01 Low...

Страница 62: ...Enabled 1 Disabled 1 STL CT2 CT0 100 Counter 2 Multiple Latch Control Register ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more information on the operating syste...

Страница 63: ...Chapter 5 Counter Timers 46 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 64: ...rchitecture figure on the following page DMA is configured through screen 2 of the BIOS SETUP utility and allows the user to set up the DMA architecture for STD 32 support For more on the BIOS SETUP u...

Страница 65: ...table Trace CT1 CT2 Frontplane DMA in Appendix A for details DMA Architecture PROGRAMMABLE REGISTERS Each DMA controller is managed through the 16 I O port addresses shown in the Slave DMA I O Port Ad...

Страница 66: ...e B D6 Write Mode Write C D8 Clear Byte Pointer Write D DA Clear Master Write E DC Clear Mask Write F DE Write Mask Write DMA Page I O Port Addressing Address Register Operation 87h Channel 0 A16 23 A...

Страница 67: ...4 3 2 1 0 Register Address Address Access Read and Write A8 A7 A6 A5 A4 A3 A2 A1 A16 A15 A14 A13 A12 A11 A10 A9 Address Register 16 bit I O See the Slave DMA I O Port Addressing table on the previous...

Страница 68: ...hannel 0 Request 0 No 1 Yes Channel 1 Request 0 No 1 Yes Channel 2 Request 0 No 1 Yes Channel 3 Request 0 No 1 Yes Access Read Status Register Command Register PRI 7 6 5 4 3 2 1 0 Register Command Sla...

Страница 69: ...10 Channel 2 11 Channel 3 Request 0 Reset 1 Set Write Request Register Write Single Mask Register 7 6 5 4 3 2 1 0 Register Single Mask Slave Address A Mask Channel MSK Master Address D4 0 0 0 0 0 MCH...

Страница 70: ...ended Mode Register ADD RSV 7 6 5 4 3 2 1 0 Register Ext Mode Slave Address 40Bh DMA Channel Select Master Address 4D6h 00 Channel 0 4 DMA TIM 01 Channel 1 5 10 Channel 2 6 11 Channel 3 7 Addressing M...

Страница 71: ...Register Clear Mask Register Register Clear Mask Slave Address E Master Address DC 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Access Write Clear Mask Register Write Mask Register MC1 7 6 5 4 3 2 1 0 Register Wri...

Страница 72: ...ister See the DMA Extended Page A24 31 I O Port Addressing table earlier in this chapter ADDITIONAL INFORMATION For more information on the operating system s use of the interrupt inputs refer to the...

Страница 73: ...Chapter 6 DMA Controller 56 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 74: ...ugh I O port locations 70h and 71h A real time clock register is accessed by first writing the offset address of the register to I O port location 70h Data is then transferred to or from the register...

Страница 75: ...10 250 ms 1111 500 ms Update In Progress 0 No 1 Yes Register A Register B Register B Address Offset 0Bh Access Read and Write SET PIE AIE UIE 0 DM 24 12 DSE 7 6 5 4 3 2 1 0 Daylight Savings 0 Disabled...

Страница 76: ...1 Interrupt Interrupt Pending 0 No interrupt 1 Interrupt Register C Register D Register D Address Offset 0Dh Access Read VRT 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Valid RAM 0 Invalid 1 Valid Register D ADDITI...

Страница 77: ...Chapter 7 Real Time Clock 60 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 78: ...ctor J5 The ZT 90205 cable assembly allows each channel to be interfaced directly to 9 pin D Shell serial devices as used in PC applications Each port may be disabled to allow for STD 32 based COM por...

Страница 79: ...d 9 pin D shell connectors The J5 connector pin assignments are accessible through the J5 Multi I O Connector topic in Appendix B PROGRAMMABLE REGISTERS There are six registers for initializing and co...

Страница 80: ...ivisor obtainable with a 16 bit integer format To guarantee proper operation the percentage error should never be greater than four Baud Rate Divisors Table Baud Rate Divisor dec hex Percent Error 50...

Страница 81: ...10 D9 D8 7 6 5 4 3 2 1 0 Divisor Latch MSB Interrupt Control Register Register Interrupt Control Address 2F9 3F9h DIV 0 Access Read and Write 0 MSI LSI TBI RBI 7 6 5 4 3 2 1 0 0 0 0 Receive Buffer Int...

Страница 82: ...Register Line Control Register 7 6 5 4 3 2 1 0 DIV BRK PTS PTE PEN STP Length Register Address Access Line Control 2FB 3FBh Read and Write Character Length 00 5 bits 01 6 bits 10 7 bits 11 8 bits Sto...

Страница 83: ...Holding Register 0 Full 1 Empty Transmit Buffer 0 Full 1 Empty Line Status Register Modem Control Register 7 6 5 4 3 2 1 0 Register Modem Control Address 2FC 3FCh Access Read and Write Data Terminal...

Страница 84: ...Clear To Send 0 Negative voltage 1 Positive voltage Data Set Ready 0 Negative voltage 1 Positive voltage Ring Indicator 0 Negative voltage 1 Positive voltage Data Carrier Detect 0 Negative voltage 1 P...

Страница 85: ...Chapter 8 Serial Controller 68 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 86: ...figuration The original PC AT Mode Also known as nibble mode because the four status bits in the cable are used for feedback from devices such as tape back up units when restoring data from a tape Sof...

Страница 87: ...may be configured for ECP mode in software DMA channel 0 is dedicated for ECP support and may be used by application software The BIOS does not use DMA for any data transfers Applications needing DMA...

Страница 88: ...to receive 1 Not ready to receive Printer Busy 0 Yes 1 No Line Printer Status Register Line Printer Control Register 7 6 5 4 3 2 1 0 Register Line Printer Control Address 37Ah Access Read and Write Da...

Страница 89: ...ormation on the parallel controller operating modes An excellent tutorial of IEEE 1284 can be obtained from FarPoint Communications 805 726 4420 The IEEE 1284 specification can be obtained from the IE...

Страница 90: ...he ZT 8905 provides a green hard disk activity light for local IDE accesses HARD DISK MOUNTING A carrier board is provided for the IDE hard disk This carrier board has a special connector that interfa...

Страница 91: ...sons The on board IDE interface addresses all of these needs although performance is equivalent to the ZT 8952 or ZT 8953 System performance however is improved because the local IDE accesses do not i...

Страница 92: ...wing topics illustrate the two System registers System Register 0 7 6 5 4 3 2 1 0 RSV RSV BUS LED VID FWP Register Address Access System Register 0 78h Read and Write Flash Memory A20 ZT8905F11REG1 Sy...

Страница 93: ...D Bus NMI Read Only 0 Active 1 Inactive STAR SYSTEM Interrupt Watchdog Timer Strobe 0 Strobe Watchdog Default 1 Arm Watchdog Reserved Register System Register 1 Address 878h Access Write Read 0 Inacti...

Страница 94: ...ust be programmed with a logical one to enable the watchdog timer to begin operation If the watchdog is allowed to expire a reset is generated If the ZT 8905 is configured as a permanent master the re...

Страница 95: ...Chapter 12 Watchdog Timer 78 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 96: ...eeping all PCI operations local Single slot occupancy capable VGA PCI OPERATION FREQUENCY The PCI operating frequency is derived from the frequency at which the Pentium CPU is operating The Pentium is...

Страница 97: ...Chapter 13 CompactPCI Mezzanine Local Bus 80 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 98: ...the LED on The LED is turned off after a power cycle or a reset The LED bit is in the same register as several system level functions It is important to preserve the state of the other bits in this re...

Страница 99: ...Chapter14 Programmable LED 82 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 100: ...1 Generic option list Options shared among all Ziatech CPUs are listed on this screen Base memory and extended memory size selection boot source hard disk type and floppy disk type are configurable th...

Страница 101: ...current parameters or ESC to quit Ziatech Industrial BIOS Setup Utility 2482 16 63 ZT8905F02 05 BIOS SETUP Utility Screen 1 Generic SETUP Options Copyright C 1997 Ziatech Corporation Interrupt from th...

Страница 102: ...lectable 000C8000h 000CFFFFh Note This region is required for STAR SYSTEM operation 000D0000h 000D7FFFh 000D8000h 000DFFFFh 00800000h 00FFFFFFh 8 Mbyte to 16 Mbyte 01000000h 03FFFFFFh 16 Mbyte to 64 M...

Страница 103: ...u to document your jumper configuration if it differs from the factory default A B C D E F W1 ZT8905FA 01 A B C D E F W1 CMOS RAM Erase Boot from Onboard Reserved Temp Master to ZT 8911 Flash Device W...

Страница 104: ...showing jumper locations W1A W1B CMOS RAM Erase W1A W1B removes the contents of the battery backed CMOS configuration RAM The CMOS RAM is erased by turning off the power and moving the W1A shorting j...

Страница 105: ...in Chapter 3 for more information on operating the ZT 8905 in a multiple master architecture W1F Temporary Master Type IN Enabled OUT Disabled W2 W3 Reserved W2 should always be installed and W3 remo...

Страница 106: ...ttable Trace Locations CT1 CT2 Frontplane DMA CT1 and CT2 assign up to two additional DMA channels for frontplane operation CT1 Function IN Connects J5 pin 53 to DMA Channel 6 DACK OUT No connection C...

Страница 107: ...Appendix A Board Configuration 90 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 108: ...ULATION RAM ALTERNATE BOOT IMAGE SOCKET FAN CON NECTOR J2 STD 32 BUS CONFIGURABLE JUMPERS MULTI I O ZT 8905 Key Parts ELECTRICAL AND ENVIRONMENTAL The following topics list electrical and environmenta...

Страница 109: ...the Ambient Temperature Vs Pentium Processor Case Temperature figure and the Pentium Processors Maximum Ambient Temperature table below Pentium Processors Maximum Ambient Temperatures Processor Speed...

Страница 110: ...s adds 0 2 A typ 0 3 A max Pentium 200 2 9 A typ 3 8 max Supply Current AUX 12 V 4 Mbyte Flash Option 0 010 A typ 0 015 A max Fan Heatsink 120 mA typ 200 mA max Battery Backup Characteristics Battery...

Страница 111: ...A9 A8 RD MEMRQ BHE ALE STATUS 0 BUSRQ INTRQ NMIRQ PBRESET INTRQ2 CNTRL PCI 2 AUX GND AUX V 5 VDC GND VBAT D3 A19 1 D2 A18 1 D1 A17 1 D0 A16 1 A7 A6 A5 A4 A3 A2 A1 A0 WR IORQ IOEXP INTRQ1 STATUS 1 BUS...

Страница 112: ...T SIDE OUTPUT DRIVE INPUT LOAD MNEMONIC E9 E11 E13 E15 E50 E52 E54 E56 DMAIOR EX8 START EX32 E58 E60 E62 E64 E57 E59 E61 E63 DMAIOW IO16 CMD EX16 E66 E68 E70 E72 E65 E67 E69 E71 T C 5 VDC MREQx MSBURS...

Страница 113: ...500 0 015 inches Board Thickness 0 158 0 018 cm 0 062 0 007 inches Board Weight Without heatsink fan 212 grams 7 5 ounces With heatsink fan 255 grams 9 ounces ZT 8906 1 004 Kilograms 2 lbs 3 4 ounces...

Страница 114: ...Revision 0 boards should refer to the Revision 0 manual for connector and cabling information Connector Assignments ZT 8905 Boards Revision A and Higher Connector Function J1 Optional L2 cache module...

Страница 115: ...STD bus loading tables Component Side Solder Side STD 32 STD 32 E01 E03 E05 E07 E09 E11 E02 E04 E06 E08 E10 E12 E71 E73 E75 E77 E79 E72 E74 E76 E78 E80 E13 E14 P01 P02 E15 E16 P03 P04 E17 E18 P05 P06...

Страница 116: ...or supplying power to the fan heatsink 12 V is used to power the fan Pin 2 is an optional Tachometer input from fans so equipped The pin assignments are given in the J2 Fan Connector Pinout table belo...

Страница 117: ...8 GND SERR GND 3 3V PAR C BE 1 GND 17 GND 3 3V SDONE SBO GND PERR GND 16 GND DEVSEL GND 5V STOP LOCK GND 15 GND 3 3V FRAME IRDY GND TRDY GND 14 GND CLK13 GND REQ4 CLK13 GNT4 GND 13 GND GNT2 CLK02 REQ3...

Страница 118: ...nd Green 8 GND Ground Blue 9 VCC 5V Option 10 GND Ground Sync 11 OPT2 VGA Opt2 12 SDA In Out VGA Data 13 HSYNC Out VGA Hor Sync 14 VSYNC Out VGA Ver Sync 15 SCL Out VGA Data Clock 16 NC No Connect J5...

Страница 119: ...ror GND Ground SLCT In Select from printer VCC 5VLED 620 ohm FPLED Out LED drive control VCC 5V Fused FPSPK Out Speaker control RSVD Factory Reserved RSVD Factory Reserved Factory Reserved Factory Res...

Страница 120: ...Signal Type Description 1 RESET Out Reset 23 IOWR Out I O Write Strobe 2 GND Ground 24 GND Ground 3 D7 In Out Data Bit 7 25 IORD Out I O Read Strobe 4 D8 In Out Data Bit 8 26 GND Ground 5 D6 In Out Da...

Страница 121: ...3 2 4 5 3 4 KEYBOARD CONN DETAIL CRIMP STRAIN RELIEF HEAT SHRINK TUBING 3 16 DIAMETER BLACK ALPHA FIT 221 3 16 SIDE VIEW 6 7 8 9 10 1 15 2 14 3 13 4 12 5 11 VIDEO CONN DETAIL AMP 748610 4 FRONT VIEW...

Страница 122: ...h com Corporate Headquarters 1050 Southwood Drive San Luis Obispo CA 93401 USA Tel 805 541 0488 FAX 805 541 5088 Central Regional Office 7700 Chevy Chase Drive Suite 110 A Austin TX 78752 USA Tel 512...

Страница 123: ...evision A 1 5 3 96 There are no functional changes between Revision A and Revision A 1 Revision A 3 6 17 97 There are no functional changes between Revision A 2 and Revision A 3 Modifications to the R...

Страница 124: ...limited warranty to its customers with a special extended warranty option Ziatech also has an explicit policy regarding the use of Ziatech products in life support systems These topics are covered in...

Страница 125: ...on In addition to the standard five year warranty Ziatech offers for a nominal fee an extended period of warranty up to five extra years This extended warranty period provides similar coverage and con...

Страница 126: ...anuals For more information on the PCI chipset implemented on the ZT 8905 refer to the Aladdin M1461 M1449 3 3 Volt Pentium Chip Set Preliminary Data Sheet Rev D or contact ALI Pacific Technology Grou...

Страница 127: ...Header Size Cache Line Timer Latency 31 16 15 0 Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Reserved Max_Lat Min_Gnt Pin Interrupt Line Interrupt 00h 04h 08h 0Ch 10h 14h 18h 1...

Страница 128: ...ter timer Counter Timers Counter Timers Overview 41 8259 interrupt controller Interrupt Controller Interrupt Controller Overview 31 8905 and 8906 comparison Introduction Product Definition Intro 1 Spe...

Страница 129: ...and Environmental Absolute Maximum Ratings 92 arbiter card ZT 89CT39 STD 32 Bus Interface Multiple Master System Requirements 28 Multiple Master and Intelligent I O Multiple Master 27 architecture Cou...

Страница 130: ...ddressing 6 Product Definition STD 32 Single Master 2 Block Diagram illus Introduction Functional Blocks Intro 4 board configuration Board Configuration BIOS SETUP Overview 83 Overview 83 Cuttable Tra...

Страница 131: ...stem Registers System Register 0 75 C cable Specifications Mechanical Cable 104 cables Specifications Cable Illus ZT 90205 Multi I O Cable 104 cache memory Introduction Functional Blocks Pentium Proce...

Страница 132: ...51 CompactPCI see PCI Introduction Functional Blocks PCI Local Bus 6 compatibility with STD 32 bus spec Getting Started System Requirements 11 STD 32 Bus Interface STD 32 Background 21 STD 32 Bus Com...

Страница 133: ...ller Interrupt Sources 33 Specifications Mechanical Connectors Intro 97 Mechanical Connectors J1 L2 Cache Module 99 Mechanical Connectors J2 Fan Connector 99 Mechanical Connectors J3 CompactPCI Local...

Страница 134: ...Counter Timers Counter Timer Operating Modes Table 42 Counter Timer Programmable Registers 42 Counter Timers Additional Information 45 Counter Timers Overview 41 Introduction Functional Blocks Counte...

Страница 135: ...teristics 93 DCE DTE Introduction Functional Blocks Serial I O 6 development considerations Introduction Development Considerations 3 device specific configuration PCI configuration space map header P...

Страница 136: ...controller DMA Controller DMA Controller Registers DMA Extended Mode Register 53 DMA extended page register DMA controller DMA Controller DMA Controller Registers DMA Extended Page Register 55 DMA Pag...

Страница 137: ...24 electrical specifications Specifications Electrical and Environmental Absolute Maximum Ratings 91 Electrical and Environmental Battery Backup Characteristics 93 Electrical and Environmental DC Ope...

Страница 138: ...ctor 101 F Factory Default Jumper Config DOS illus Board Configuration Jumper Options Illus DOS Factory Default Config 86 fan heatsink Getting Started System Requirements 11 Specifications Mechanical...

Страница 139: ...ntroduction Functional Blocks Intro 4 functional blocks Introduction Functional Blocks Counter Timers 7 Functional Blocks DMA 7 Functional Blocks IEEE 1284 Parallel Port Interface 8 Functional Blocks...

Страница 140: ...Hard Disk Connector 103 hard disk mounting Optional IDE Interface Hard Disk Mounting 73 header configuration PCI PCI Configuration Space Map Overview 109 heatsink fan Getting Started System Requiremen...

Страница 141: ...6 Mechanical Connectors J7 IDE Hard Disk Connector 103 IEEE 1284 parallel port interface IEEE 1284 Parallel Port Interface Address Mapping 70 DMA Selection 70 IEEE 1284 Parallel Port Interface Overvie...

Страница 142: ...Parallel Port Interface Interrupt Selection 70 interrupt architecture illustration Interrupt Controller Interrupt Architecture Illustration 32 interrupt control register serial controller Serial Cont...

Страница 143: ...e STD Bus Interrupts Intro 24 STD 80 Peripheral Support Interrupts 22 System Registers System Registers System Register 1 76 Watchdog Timer Watchdog Timer Operation 77 introduction to ZT 8905 Introduc...

Страница 144: ...upt Sources 33 Introduction Functional Blocks IEEE 1284 Parallel Port Interface 8 J5 Multi I O Connector Illustration 8 Serial Controller ZT 8905 Specifics 61 Serial Channel Interface 62 Specification...

Страница 145: ...88 Getting Started Jumper Descriptions 16 jumper locations Board Configuration Jumper Options and Locations Intro 85 K keyboard controller local or VGA Introduction Functional Blocks Keyboard Control...

Страница 146: ...atus register IEEE 1284 parallel port interface IEEE 1284 Parallel Port Interface Parallel Port Interface Line Printer Status Register 71 line status register serial controller Serial Controller Seria...

Страница 147: ...ess Map 13 memory addressing configuration Getting Started Memory Configuration 12 Introduction Functional Blocks Memory and I O Addressing 6 STD 32 Bus Interface STD 32 Bus Compatibility Extended Arc...

Страница 148: ...I O Connector J5 ZT 90205 multi I O cable Serial Controller Serial Channel Interface 62 multiple latch control register illustration Counter Timers Counter Timer Multiple Latch Control Register 45 mul...

Страница 149: ...om Onboard Flash 87 operating modes Counter Timers Counter Timer Operating Modes Table 42 operating system installation Getting Started Operating System Installation 19 operating temperature Specifica...

Страница 150: ...Parallel Port Interface Programmable Registers 70 Introduction Functional Blocks IEEE 1284 Parallel Port Interface 8 parallel port modes IEEE 1284 Parallel Port Interface Parallel Port Configuration O...

Страница 151: ...el Port Interface 8 product definition Introduction Product Definition Intro 1 Product Definition Stand Alone Operation 1 Product Definition STD 32 Mult Master STAR SYSTEM 2 Product Definition STD 32...

Страница 152: ...ister B real time clock Real Time Clock Real Time Clock Registers Register B 58 register C real time clock Real Time Clock Real Time Clock Registers Register C 59 register D real time clock Real Time...

Страница 153: ...ter ICW2 Illustration 35 Initialization Register ICW3 Illustrations 35 Initialization Register ICW4 Illustration 36 Interrupt Controller Extended Mode Register 40 Interrupt Controller Initialization R...

Страница 154: ...tomer Support Returning for Service 107 revision 0 differences Specifications Mechanical Connectors Intro 97 revision history Customer Support Revision History 105 RMA Return Material Authorization Cu...

Страница 155: ...d Configuration BIOS SETUP Overview 83 ZT 8905 Specific SETUP Options 85 Getting Started Operating System Installation 19 System Configuration Overview 17 ZT 8905 Setup 16 Introduction Functional Bloc...

Страница 156: ...oduct Definition Stand Alone Operation 1 standard architecture SA STD 32 Bus Interface STD 32 Bus Compatibility Standard Architecture 22 STAR SYSTEM Introduction Development Considerations 3 Functiona...

Страница 157: ...STD 32 Background 21 STD 32 Bus Compatibility Compliance Levels 23 STD 32 Bus Compatibility Extended Architecture 23 STD 32 Bus Compatibility Intro 22 STD 32 Bus Compatibility Multiprocessing 23 STD...

Страница 158: ...m Installation 19 System Configuration Overview 17 ZT 8905 Setup 16 system registers System Registers System Registers Overview 75 System Registers Programmable Registers 75 System Registers System Re...

Страница 159: ...VGA Transition Connector 101 transmit buffer serial controller Serial Controller Serial Controller Register Addressing Table 62 V VGA interface Specifications Mechanical Connectors J4 VGA Transition C...

Страница 160: ...ation Jumper Descriptions W2 and W3 Reserved 88 warranty Customer Support Warranty Intro 107 watchdog timer Introduction Functional Blocks Watchdog Timer 7 System Registers System Registers System Reg...

Страница 161: ...etting Started Operating System Installation 19 System Configuration Overview 17 ZT 8905 Setup 16 zPM10 Super VGA Interface Introduction Functional Blocks PCI Local Bus 6 Specifications Mechanical Con...

Страница 162: ...Interface Multiple Master System Requirements 28 Multiple Master and Intelligent I O Multiple Master 27 ZT 90205 multi I O cable Introduction Functional Blocks IEEE 1284 Parallel Port Interface 8 Spec...

Страница 163: ...Index xxxvi Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 164: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 165: ...se Drive Suite 110 A 319 North Pottstown Pike Suite 107 P O Box 110 Austin TX 78752 USA Exton Pennsylvania 19341 USA AC SON Tel 512 458 3177 Tel 610 524 9070 Netherlands 5690 FAX 512 458 3178 FAX 610...

Страница 166: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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