Ziatech Corporation ZT 8905, Руководство по оборудованию

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Chapter 3. STD Bus Interface
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SDMA16, SDMA8 Supports 8-bit or 16-bit Standard Architecture DMA as defined in the
STD 32
Bus Specification and Designer's Guide . Control signals are provided through
the frontplane connector.
SDMABP Supports Standard Architecture DMA using BUSRQ*/BUSAK* for request and
acknowledge and the backplane DMA control signals DMAIOR*, DMAIOW*, and
T-C.
STD BUS INTERRUPTS
The ZT 8905 supports both maskable and non-maskable interrupts from the STD bus. This section
discusses system level issues related to these interrupts. Refer to Chapter 4, "Interrupt Controller" for
more information on the maskable interrupt controllers.
Maskable Interrupts
The STD bus maskable interrupts monitored by the ZT 8905 are INTRQ* (P44), INTRQ1* (P37),
INTRQ2* (P50), INTRQ3* (E67), and INTRQ4* (P6). These maskable interrupts are configurable
through the BIOS SETUP mechanism.
The ZT 8905 is also capable of generating STD bus or frontplane interrupts. This feature is useful in
multiple master systems to coordinate communications between processors. Typically, INTRQ4* is
used for this feature in STD 32 STAR SYSTEMs.
Some applications may find it necessary to share multiple interrupt sources on a single STD bus
interrupt request, as shown on the following page in the "STD Bus Polled Interrupt Structure"
illustration. Since the interrupt controller provides a single vector for each input, it is up to the
application software to poll each possible source on the shared interrupt request signal to determine
which is requesting service. This procedure is fine for most applications, provided that each source
can be polled and that the interrupt controller is programmed for level-triggered operation.
Some applications include edge-triggered interrupt sources. For example, the Ziatech DOS System
uses edge-triggered interrupts to support the timer used to generate the periodic system tick.
Normally, the 8259 interrupt controller inputs are not independently programmable for edge-triggered
or level-triggered interrupts, all inputs for these applications must be treated as edge-triggered. The
ZT 8905 uses an enhanced version of the 8259 interrupt controller which does allow individual
interrupt levels to be configured.
In an edge-triggered architecture, multiple interrupt sources should not share the same interrupt
request signal because it is possible to miss an interrupt request from one source while an interrupt
request from another source is being serviced. For this architecture, each interrupt source requires a
unique connection to the interrupt controller, as shown in the "STD Bus Vectored Interrupt Structure"
illustration on the following page.
The ZT 8905 can have up to 10 independent interrupt sources from off-board devices (5 from the
backplane, 5 from the frontplane). Note that normally, some of the available interrupt controller inputs
are reserved for on-board use, which may limit availability for off-board peripherals. For example, if
the on-board COM ports are being used, then IR3 and IR4 are not available for off-board use.
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