Ziatech Corporation ZT 8905, Руководство по оборудованию

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Contents
STD 32 BUS COMPATIBILITY ................................................................................................ 22
Standard Architecture ................................................................................................. 22
Extended Architecture................................................................................................. 23
Multiprocessing ........................................................................................................... 23
STD 32 Compliance Levels ........................................................................................ 23
STD BUS INTERRUPTS ......................................................................................................... 24
Maskable Interrupts .................................................................................................... 24
Non-Maskable Interrupts ............................................................................................ 26
RESET ..................................................................................................................................... 26
MULTIPLE MASTER AND INTELLIGENT I/O......................................................................... 26
Multiple Master............................................................................................................ 27
Intelligent I/O ............................................................................................................... 27
Multiple Master Vs. Intelligent I/O ............................................................................... 28
Multiple Master System Requirements ....................................................................... 28
Multiple Master Reset ................................................................................................. 30
CHAPTER 4. INTERRUPT CONTROLLER ......................................................................................... 31
INTERRUPT SOURCES.......................................................................................................... 33
PROGRAMMABLE REGISTERS ............................................................................................ 33
Initialization Registers (ICW1-ICW4) .......................................................................... 34
Initialization Register ICW1 .................................................................................. 35
Initialization Register ICW2 .................................................................................. 35
Initialization Register ICW3 .................................................................................. 35
Initialization Register ICW4 .................................................................................. 36
Operational Registers (OCW1-OCW3) ...................................................................... 36
Operational Register OCW1 ................................................................................ 36
Operational Register OCW2 ................................................................................ 37
Operational Register OCW3 ................................................................................ 38
Status Registers (IRR, ISR, IPR) ................................................................................ 38
Status Register IRR.............................................................................................. 38
Status Register ISR .............................................................................................. 39
Status Register IPR .............................................................................................. 39
Extended Mode Register ............................................................................................ 40
ADDITIONAL INFORMATION ................................................................................................. 40
CHAPTER 5. COUNTER/TIMERS ....................................................................................................... 41
PROGRAMMABLE REGISTERS ............................................................................................ 42
Count Registers and Count Latch............................................................................... 42
Status Register ........................................................................................................... 43
Control Register .......................................................................................................... 44
General Control Register...................................................................................... 44
Count Latch Control Register ............................................................................... 44
Multiple Latch Control Register ............................................................................ 45
ADDITIONAL INFORMATION ................................................................................................. 45
CHAPTER 6. DMA CONTROLLER ..................................................................................................... 47
ZT 8905 SPECIFICS................................................................................................................ 47
PROGRAMMABLE REGISTERS ............................................................................................ 48
Address Register ........................................................................................................ 50
Count Register ............................................................................................................ 50
Status Register ........................................................................................................... 51
Command Register..................................................................................................... 51
Write Request Register............................................................................................... 52
Write Single Mask Register ........................................................................................ 52
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