Ziatech Corporation ZT 8905, Руководство по оборудованию

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Chapter 3. STD Bus Interface
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Interrupts
The STD-80 Series Bus Specification defines a single interrupt signal, INTRQ* (P44). If STD bus
maskable interrupts are used in the application, the ZT 8905 is configurable to receive INTRQ* and
four optional interrupts: INTRQ1* (P37), INTRQ2* (P50), INTRQ3* (E67), and INTRQ4* (P6).
STD bus peripheral boards must be capable of generating an interrupt on INTRQ1*, INTRQ2*,
INTRQ3*, and INTRQ4* to use this feature.
I/O Expansion
The STD-80 Series Bus Specification defines an I/O expansion signal, IOEXP, used to reduce
addressing redundancy of an I/O board decoding fewer than 16 address lines. The ZT 8905
automatically drives this signal low when the application software performs an STD bus I/O address
in the address range FC00h through FFFFh. To use this feature:
•
The I/O mapped STD bus board is configured to respond to an active low IOEXP.
•
The application software assigns the board to address FC00h plus the board configuration offset.
DMA Slave Support
The ZT 8905 supports DMA slaves through either backplane or frontplane signaling. The STD 32
specification defines control signals for backplane DMA transfers to peripherals such as the ZT 8954
Floppy Disk Interface. The ZT 8905 supports up to three DMA slaves controlled via a 10-pin
frontplane header provided by the ZT 90205 cable.
STD 32 BUS COMPATIBILITY
The ZT 8905 is compatible with the
STD 32 Bus Specification and Designer's Guide
(Ziatech part
number ZT MSTD32). The STD 32 bus allows both older STD-80 style peripherals and new higher
performance peripherals as defined by STD 32 to be used in the same backplane. STD 32 separates
older peripherals and newer peripherals into Standard Architecture, Extended Architecture, and
Multiprocessing, as described in the following topics.
Standard Architecture
Standard Architecture 8- and 16- bit peripherals are referred to as SA8 and SA16, respectively. The
ZT 8905 supports interfacing to both SA8 and SA16 peripherals. Older STD-80 style peripherals are
compatible with SA8 transfers, allowing the ZT 8905 to support these peripherals. The ZT 8905
automatically determines the type of transfer at the start of each STD bus operation. If the application
software includes a 16-bit operation with an 8-bit STD bus (SA8) board, the ZT 8905 automatically
reduces the transfer into two STD bus cycles. If the application software includes a 16-bit operation
with a 16-bit STD 32 (SA16) board, the ZT 8905 performs the transfer in a single STD bus cycle. A
single STD cycle for SA peripherals is typically seven STD 32 clock periods.
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