Appendix D. PCI Configuration Space Map
110
ZT8905FD01
Base Address Registers
Cardbus CIS Pointer
Vendor ID
Device ID
Status
Command
Class Code
Revision ID
BIST
Type
Header
Size
Cache Line
Timer
Latency
31
16
15
0
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Reserved
Max_Lat
Min_Gnt
Pin
Interrupt
Line
Interrupt
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
O
F
F
S
E
T
S
PCI Configuration Header
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Содержание ZT 8905
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