CHAPTER 6. DMA CONTROLLER
This chapter provides an overview of ZT 8905 DMA architecture and DMA controller operation.
Descriptions of DMA controller programmable registers are also included.
ZT 8905 SPECIFICS
The ZT 8905 includes two cascaded, Intel-compatible, 8237 Direct Memory Access controllers that
provide a programmable interface for direct transfers between peripherals and main memory. Seven
channels of DMA are supported, with up to four devices located on the STD 32 bus. The DMA
controllers used on the ZT 8905 are supersets of the 8237 device, supporting 32-bit memory
accesses, higher speed transfers, and the PCI protocol. Features of the DMA controllers include:
•
8237 Compatible/superset
•
Seven DMA Channel support
•
32-bit memory addressing
•
Compatible, TYPE A, TYPE B, TYPE F transfer rates
•
Fixed or rotating priorities
•
PCI Bus mastering
The DMA architecture is illustrated in the "DMA Architecture" figure on the following page. DMA is
configured through screen 2 of the BIOS SETUP utility and allows the user to set up the DMA
architecture for STD 32 support. For more on the BIOS SETUP utility, see the section "BIOS SETUP
Overview" in Appendix A..
Backplane:
DMA service is available for the BUSRQ*/BUSAK signals on the STD 32 backplane.
Normally, these signals are used for backplane floppy disk controller servicing via DMA
channel 2. If a floppy disk controller is not used in the system, SETUP alternately
allows BUSRQ*/BUSAK* to be serviced by DMA Channel 5 for 16-bit peripherals. If the
floppy disk controller is enabled in SETUP, only DMA Channel 2 is allowed for
BUSRQ*/BUSAK*.
Frontplane:
Three channels of DMA are supported via the Multi-I/O connector (J5). Channels 1, 6,
and 7 can be used by STD 32 peripherals for DMA servicing.
Local:
The on-board IEEE 1234 Parallel Port can be configured to use DMA channel 0 for
data transfers. The Parallel Port must be configured for ECP mode to use DMA.
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Содержание ZT 8905
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