CHAPTER 12. WATCHDOG TIMER
The primary function of the watchdog timer is to monitor ZT 8905 operation and take corrective action
if the system fails to function as programmed. The major features of the watchdog timer are listed
below.
•
Single-stage
•
Enabled and disabled through software control
•
Armed and strobed through software control
WATCHDOG TIMER OPERATION
The watchdog timer architecture is illustrated in the "Watchdog Timer Architecture" figure below. The
watchdog timer is implemented in the Dallas Semiconductor DS1232 system monitor.
After power on or reset, the watchdog function is disabled, meaning that the watchdog is continually
being strobed by an 8 MHz signal. Bit 0 of System Register 1 (878h) must be programmed with a
logical one to enable the watchdog timer to begin operation. If the watchdog is allowed to expire, a
reset is generated. If the ZT 8905 is configured as a permanent master, the reset extends to the STD
bus. If the ZT 8905 is configured as a temporary master, the reset remains local. To strobe the
watchdog, Bit 0 of System Register 1 (878h) must be written with a logical 0 and then a logical 1.
The watchdog timeout period is fixed at 500 ms minimum and 2000 ms maximum. Software must
strobe the watchdog timer within 500 ms to guarantee that the system is not reset.
System Register 1
(878h, Bit 0)
(DS 1232)
8MHz
Reset
WatchDog Timer Architecture
ADDITIONAL INFORMATION
Refer to the Dallas Semiconductor DS1232 data sheet for more information on the watchdog timer
and the associated operating modes.
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Содержание ZT 8905
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