Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Interrupt Controller (8259A)
OCW1
OCW1 is used solely for 8259A masking operations. It is located at
I/O address 21h. It provides a direct link to the IMR (Interrupt Mask
register). The processor can write to or read from the IMR via
OCW1. The OCW1 bit definition is as follows:
M0-M7 The M0-M7 bits are used to control the masking of
interrupt request (IR) inputs. If an M bit is set to 1, it
masks the corresponding IR input. A logical 0 clears the
mask, thus enabling the IR input. These bits convey the
same meaning when being read by the processor for
status update.
OCW2
OCW2 is used for End-Of-Interrupt, automatic rotation, and specific
rotation operations. It is located at I/O address 20h. Associated
commands and modes of these operations, with the exception of
AEOI initialization, are selected using the bits of OCW2 in a
combined fashion. Selection of a command or mode should be made
with the corresponding table for OCW2, shown in Figure 12-4 on
page 12-17, rather than on a bit-by-bit basis.
However, for
completeness of explanation, bit definition of OCW2 is as follows:
L0-L2 The L0-L2 bits are used to designate an interrupt level
(0-7) to be acted upon for the operation selected by the
EOI, SL, and R bits of OCW2. The level designated is
used either to reset a specific ISR bit or to set a specific
priority. The L0-L2 bits are enabled or disabled by the
SL bit.
12-18