Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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ZT 88CT08A/88CT09A CMOS Boards
If you take advantage of the Clock Slowdown feature, typical power
consumption is reduced to 132 mA with one 64 Kbyte EPROM and
one 128 Kbyte RAM and a 100 pF load on the STD bus. This shows a
power reduction of approximately 30 percent.
To further reduce power, use the halt with interrupt restart method
(see page 3-29). During the time the processor is halted, power con-
sumption measures 115 mA with the same memory configuration and
capacitive load.
This provides a power reduction of roughly
40 percent from the typical value.
Bus Loading
Since power consumption and delay times for CMOS logic are
directly proportional to load capacitance, it is important to pay
particular attention to
bus loading. The ZT 88CT08A and
ZT 88CT09A are designed for a bus capacitance of 300 pF. If the
STD bus system presents a greater load than this to the processor
board, you should slightly modify the timings shown in Appendix A
to compensate for this.
13-9