Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Getting Started
MEMORY ADDRESSING
Figures 2-3 and 2-4 on pages 2-20 and 2-21 show the memory
addresses occupied by the ZT 8809A, for both STD DOS and
STD ROM.
See also Appendix A for the tables describing the
memory configuration jumpers W55-W59.
Access to on-board memory and the backplane is through the full
8088 20-bit memory address, allowing for 1 Mbyte of memory in the
system. On-board memory consists of one 32 Kbyte static RAM and
four 32-pin byte-wide sockets. Two of these sockets accept from 32K
to 256 Kbyte EPROMs.
The other two accept either 128K or
512 Kbyte RAMs. One of the EPROM sockets may also be config-
ured for static RAM. All RAM may be battery-backed.
Memory access times required are 380 ns for a ZT 8808A and 210 ns
for a ZT 8809A. If DMA to or from on-board memory is used, chip
access times remain the same. If one wait state is inserted, add one
clock cycle to these speeds (access times then become 550 ns for a
ZT 8808A and 325 ns for a ZT 8809A).
Memory access times for ZT 8808A/8809A boards are as follows.
Revision A
ZT 8808A 380 ns or less (any access)
ZT 8809A 210 ns or less (any access)
Because a relatively fast speed is required for EPROM on the
ZT 8809A, be sure to verify the access times for the devices used on
your ZT 8809A if the board is jumpered for no wait states. Adding
one wait state improves your device access time by 125 ns, thereby
allowing use of the slower parts.
2-19