Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Serial Communications (16C452)
Modem Control Register
(2FCh, 3FCh; R/W)
The Modem Control register (MCR) controls the interface with the
modem or data set (or a peripheral device emulating a modem). The
contents of the MCR are included in Table 8-3 on pages 8-18 and
8-19 and are described below. The RTS* and DTR* outputs are
directly controlled by their control bits in this register. A high written
to these bits asserts the signal active (low) at the output.
Bit 0 This bit controls the Data-Terminal-Ready (DTR*)
output. Setting this bit to 1 asserts the DTR* output
active (low). By resetting this bit to 0, the DTR* output
is set inactive (high).
Bit 1 This bit controls the Request-To-Send (RTS*) output.
When bit 1 is set to logical 1, the RTS* output is set
active (low). When bit 1 is reset to logical 0, the RTS*
output is set inactive (high).
Bit 2 This bit would normally control the Output 1 (OUT1)
signal, which is an auxiliary user-designated output. The
VL 16C452 implementation of the 16C452 serial port
OUT1 is not connected to an output pin.
Bit 3 This bit normally controls the Output 2 (OUT2) signal
on a 16C450, which is an auxiliary user-designated
output. In this implementation of the 16C452, this signal
controls the output enable to the buffered interrupt
request from the associated interrupt controller. Writing
a 1 to this bit enables the interrupt output, and writing a 0
three-states it. This is implemented identically to the
IBM PC/XT serial port, making these serial ports fully
IBM compatible. We recommend that this bit be set to 1
prior to enabling the associated interrupt input at the
8259 Interrupt Controller on board.
8-31