Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Serial Communications (16C452)
Bit 5 This bit is the complement of the Data-Set-Ready
(DSR*) input. When set, this bit indicates that the
modem is ready to provide received data to the serial
channel receiver circuitry. When DSR* is active
(low), this bit is set to 1. If the channel is in the
loopback mode, this bit is equivalent to DTR in the
MCR.
Bit 6 This bit is the complement of the Ring Indicator
(RI*) input. If the channel is in the loopback mode,
this bit doesn’t reflect any MCR bit status.
Bit 7 This bit is the complement of the Received Line
Signal Detect (RLSD*) input. If the channel is in the
loopback mode, this bit is equivalent to OUT2 of the
MCR.
The modem status inputs (-RI, -RLSD, -DSR, and -CTS) reflect or
are activated by any change of status. Reading the MSR clears these
indications but has no effect on the status bits. The status bits reflect
the state of the input pins, regardless of the mask control signals. If a
DCTS, DDSR, TERI, or DRLSD is true, and a state change occurs
during a read operation (-DISTR), the state change is not indicated in
the MSR. If DCTS, DDSR, TERI, or DRLSD is false, and a state
change occurs during a read operation, the state change is indicated
after the read operation.
For LSR and MSR, the setting of status bits is inhibited during status
register read -DISTR operations. If a status condition is generated
during a read -DISTR operation, the status bit is not set until the
trailing edge of the read -DISTR.
If a status bit is set during a read -DISTR operation, and the same
status condition occurs, that status bit is cleared at the trailing edge of
the read -DISTR instead of being set again.
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