Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Counter/Timers (8254)
The Status register shown in Figure 11-2, when latched, contains the
current contents of the Control Word register and status of the output
and null count flag. See the description of the Read-Back command
on page 11-11.
The OLM and OLL are two 8-bit latches. OL represents "Output
Latch" and M and L refer to the high and low bytes of the count,
respectively. These latches contain the count presently attained in the
Counting Element (CE). However, if the Counter Latch command is
sent to the 8254, then the OL high and low contain the count latched
by that command until read by the CPU. The CE can never be read,
but the OL latches reflect the value in the CE.
Similarly, there are two 8-bit registers called CRM and CRL. CR
represents "Count Register" and M and L again refer to the high and
low bytes, respectively. When a new count is written to the counter, it
is first stored in the CR high and low bytes one byte at a time and
later transferred to the CE as a 16-bit word. The CRM and CRL are
cleared when the counter is programmed.
The CLK, GATE, and OUT signals represent the clock input, enable
input, and timer output, respectively. On the ZT 8809A, the CLK
input on counter 0 is always 1.19318 MHz, equal to the IBM PC/XT
frequency of 4.77 MHz divided by four. This frequency is supplied by
an on-board oscillator that is independent of the microprocessor
speed. Counters 1 and 2 CLK inputs are selectable between the
1.19318 MHz oscillator and an input tied to the frontplane connector
J3.
The GATE inputs of all three timers are pulled up to the active (high)
state and are also routed to the connector J3 for off-board control. All
counter OUT signals are routed both to the 8259A interrupt controller
and to the connector J3. For details on the possible interrupt request
levels for these timers, refer to Chapter 12.
11-5